Cadence Seeking Papers for CDNLive Silicon Valley 2013 Users Conference

Cadence CDNLive Silicon Valley 2013 Users Conference

Cadence Design Systems has issued a call for papers for the CDNLive Silicon Valley 2013 Users Conference. Cadence is seeking presentations and papers on design topics that illustrate users’ experiences with Cadence products, solutions, flows, methodologies, and techniques. The deadline for paper submission is December 4, 2012. Selected papers will be presented at CDNLive Silicon Valley. The event runs March 12-13, 2013 at the Hyatt Regency in Santa Clara, California.

Cadence is seeking CDNLive papers on:

  • Cadence Technologies
    Papers should share experiences with Cadence technology and illustrate exciting ways in which design and verification teams have successfully used these technologies on their most recent projects

  • Design Methods/Case Studies
    Papers should describe innovative methodologies or specific examples that highlight design flows using Cadence methodologies to develop cutting-edge silicon, SoCs, and full systems

  • Design Techniques
    Papers should describe interesting and innovative design experiences related to specific design projects. These submissions should be more “how to” in nature and include a brief description of the design and discuss methodology, flow, and innovative use models

CDNLive Topics of Interest

  • Advanced and high-performance noise analysis for switching circuits
  • Analog/mixed signal design
  • Verification planning
  • Voltage drop/electromigration
  • Memory: DDR/DDR2/DDR3/DDR4/Wide IO
  • Non-Volatile Memory/Flash
  • Connectivity: PCI Express, Ethernet, USB
  • SerDes/PHY/MAC
  • Advanced clocking strategies for managing power and variability
  • Advanced node (32nm, 28nm, 20nm) SoC implementation
  • Timing constraints verification
  • Verification of integration-ready IP
  • Analog/mixed-signal SoC verification
  • Assertion-based verification/formal analysis
  • Verification of low-power design structures
  • Verification planning and management
  • Chip-Package-Board System Prototyping
  • Chip-Package-Board System Signal and Power Analysis
  • Silicon/package co-design
  • Simulation model development
  • Low-power design methodologies and flows
  • Low-power design techniques or design techniques and flows for ultra power savings
  • Power estimation methodologies and flows
  • Analog, mixed-signal behavioral modeling
  • Analog, mixed-signal, and RF design methodologies and flows
  • Metric driven verification for analog and mixed-signal design
  • OA based interoperability flow between Virtuoso and Encounter
  • Design for test and manufacturing
  • DFY/DFM optimization techniques and results
  • Working with foundries
  • Yield optimization (linking design and fab)
  • Embedded software development and verification
  • FPGA-based prototyping
  • System design, integration and emulation
  • Verification IP

More info: CDNLive Silicon Valley 2013