Analog Devices Debuts AD9559 Quad-input Adaptive Clock Translator IC

AD9559 quad-input multiservice line card adaptive clock translator IC

Analog Devices announced the AD9559 integrated circuit. The AD9559 is a fully-programmable, jitter-attenuating, dual-clock translator IC. The chip simultaneously supports different standard frequencies for wired communications applications, including synchronous Ethernet, SONET/SDH, 1/10/100G Ethernet, Fiber Channel, and other applications that require low jitter, flexibility and fast time-to-market. The ADI AD9559 is available now in 10mm x 10mm, 72-lead LFCSP packaging. It is priced at $19.26 each in 1,000 quantity.

The AD9559 synchronously converts any standard input frequency to any standard output frequency at up to 1.25 GHz with sub-400-fs RMS (root mean square) total jitter over a 12-kHz to 20-MHz integration bandwidth. The AD9559 quad-input multiservice line card adaptive clock translator replaces two synchronous timing devices with a single IC.

The AD9559 continuously generates a clean (low jitter) valid output clock, even when all references have failed, by means of a digitally-controlled loop and holdover circuitry. The built-in programmability of the AD9559 clock translator allows network line card designers to use the same component in many different board designs, limiting the number of components needed and reducing overall system cost.

The AD9559 adaptive clock translator is ideal for data communications, next-generation wired networking applications, test and measurement, high-speed data acquisition, video applications, and wireless base station controllers.

ADI AD9559 Quad-input Dual Adaptive Clock Translator Features

  • Dual DPLL architecture, with four reference inputs (single-ended or differential) going to an input crosspoint
  • Parallel DPLL architecture for generating output clocks that are completely independent of each other
  • Each of the two DPLLs can be synchronized to one of up to four input references
  • Each DPLL generates two output clocks
  • Supports adaptive clocking and gapped clock input reference for OTN de-mapping applications
  • Supports GR-1244 Stratum 3 stability in holdover mode
  • Smooth reference switchover with virtually no disturbance on output phase
  • Frequency at the output to be dynamically adjusted over a ±100 ppm range
  • Frequency step as low as sub-0.1 ppb at nominal output frequency
  • Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems
  • Supports ITU-T G.8262 Synchronous Ethernet slave clocks
  • Supports ITU-T G.823, G.824, G.825, and G.8261
  • 10mm x 10mm, 72-lead LFCSP packaging
  • Ideal for data communications, next-generation wired networking applications, test and measurement, high-speed data acquisition, video applications, and wireless base station controllers

More info: AD9559 Dual PLL Quad Input Multiservice Line Card Adaptive Clock Translator (pdf)