ASSET InterTech published a new white paper about non-intrusive embedded instruments. The technical paper explains how non-intrusive software-driven embedded instruments can overcome many of the challenges of testing, validating and debugging high-speed memory buses such the DDR 3 or DDR4 (DDR3/4) buses, and others. The title of their article is “How to test high-speed memory with non-intrusive embedded instruments.”
The memory test white paper describes the engineering tradeoffs involved with several non-intrusive test methods, including processor-controlled test (PCT), FPGA-controlled test (FCT), memory built-in self test (MBIST), boundary-scan test (BST) and functional test. The 21-page article is written by Al Crouch, ASSET’s chief technologist for core instrumentation and vice-chairman of the working group developing the IEEE P1687 Internal JTAG (IJTAG) standard for embedded instruments.
How to test high-speed memory with non-intrusive embedded instruments
A recent survey of engineers in the electronics industry by the International Electronics Manufacturing Initiative (iNEMI) found that testing memory and memory buses on circuit boards is one of the most pressing problems for system manufacturers. A number of factors has contributed to this problem; namely, the disappearance of test pads on circuit boards for in-circuit test (ICT) bed-of-nail fixtures, restrictions on placing any sort of a test probe on high-speed memory buses because of the capacitive signal distortion created by the probe, increasingly complex memory bus protocols and others.
Fortunately, there are a number of non-intrusive board test (NBT) or probe-less methods for testing memory, including boundary-scan test (BST), functional test, processor-based testing methodologies such as processor-controlled test (PCT), FPGA-based testing mechanisms such as FPGA-controlled test (FCT) and embedded memory built-in self-test (memory BIST). Each method has advantages and disadvantages over the others. As is typical in the electronics industry, choosing any one method will involve tradeoffs. This white paper describes these various methods and explains some of the most salient tradeoffs. In particular, some of the complexities involved with testing the high-speed DDR (Double Data Rate) memory bus will be explained.
More info: ASSET InterTech Memory Test White Paper