The DFI 3.1 specification was released by the DDR PHY Interface (DFI) Group. The DFI industry specification defines an interface protocol between DDR memory controllers and PHYs. The DDR PHY Interface specification enables the development of systems-on-chip (SoCs) that support the DDR3 and DDR4 memory standards. The preliminary DFI 3.1 memory specification is available now for download.
Version 3.1 of DFI features support for the LPDDR3 mobile memory standard for smartphones and tablets. It also includes enhancements to the low-power interface and training features. The DFI interface standard was developed through the collaborative effort of leaders in the semiconductor and EDA markets and has become the de facto industry standard for high-bandwidth memory interfaces.
DFI 3.1 is a memory interface standard that enables the interoperability of IP between different companies. It defines methods for interfacing to DDR4 devices (with data rates up to 3.2 Gbits/second per pin) and LPDDR3 devices (with data rates up 6.4 Gbits/sec. and 12.8 Gbits/second for a dual channel configuration). The standard has been recognized by JEDEC, the microelectronics industry’s open standards organization.
In other news, Cadence Design Systems announced that their suite of DDR controller and DDR PHY design IP as well as its Cadence Verification IP Catalog now support version 3.1 of the DFI specification. With the addition of support for LPDDR3 memory, the DFI standard can now be used in the development of SoCs targeting smartphone and tablet applications that require higher-bandwidth memory.