Cadence Design Systems introduced a new full-featured NVM Express interface subsystem. It is the industry’s first IP subsystem for the development of SoCs that support the NVM Express 1.0c standard, which is an interface technology used for solid-state drives (SSD). With Cadence’s IP subsystem, SoC designers do not need to source their interface component IP separately and drive integration on their own. The new subsystem approach decreases design risk and overall development time for new SoCs.
The new IP subsystem solution includes Cadence Design IP for NVM Express controller and Cadence Design IP for NVM Express subsystem. The subsystem is the industry’s first to feature fully-integrated component IP, including the NVM Express Controller, firmware, and the corresponding NVMe and PCIe models from the Cadence Verification IP Catalog. This high level of integration enables easy implementation of NVM Express in SoC designs.
The Cadence NVM Express controller supports advanced command management, data tiering and hardware command acceleration. The IP is highly configurable, allowing it to target the broad scope of applications possible with NVM Express. The included driver firmware offers an easy interface to the system firmware. The solution also includes a verification and test environment spanning from the PCI Express interface to the internal bus fabric.
NVM Express is a specification that will speed the broader adoption of PCI Express-based SSDs. It improves performance and reduces power consumption and latency compared to existing SATA/SAS interfaces or proprietary PCI Express implementations. The NVM Express specification defines the register interface, command set, and feature set to provide a scalable interface for PCI Express-based SSDs.
More info: Cadence Design Systems, Inc.