SEMATECH Presents Research Papers at VLSI-TSA Symposium

SEMATECH recently presented nine research papers at the International VLSI Technology, System and Applications Symposium (VLSI-TSA). The SEMATECH researchers reported on innovative materials and new transistor structures to address key aspects of transistor performance, power, and cost. The white papers outlined leading-edge research in high-k/metal gate (HKMG) materials, resistive RAM (RRAM) memory, and planar and non-planar CMOS technologies.

According to Sitaram Arkalgud, director of SEMATECH’s 3D interconnect program, one potentially industry-changing technology is a direct metal bonding interconnect approach. SEMATECH’s copper-to-copper direct bonding (CuDB) technology is a promising technology to aggressively scale chip-to-chip interconnects and keep pace with advances in TSV. In order for 2.5D and 3D integration to reach its full potential, chip-to-interposer and chip-to-chip interfaces have to support a very large number of power and signal connections. Today, most solder-based interconnect schemes will not scale sufficiently due to mechanical, electrical, thermal, and reliability limitations.

SEMATECH’s VLSI-TSA Technical Papers Highlights

Silicon Channel Devices

  • Evaluating stress-induced leakage current (SILC) in full gate-last (FGL) high-k/metal gate devices to address sources of SILC and propose possible process options for improvement. A high quality interlayer during gate stack formation was found to be critical to improving FGL device performance and reliability.
  • Modeling positive bias temperature instability (PBTI) degradation in Zr-doped HfO2 gate stacks by considering fast and slow electron trapping processes. PBTI was found to improve when the fast trapping component was suppressed.

Non-Silicon Channel Devices

  • Using different ALD oxidizers to study the effects of III-V oxides on device performance. With a O3 precursor, As-As, AsOx, GaO, and In2O3 were found to be the main native oxides/byproducts. H2O-based precursors remain stable with no III-V oxide detected throughout a low temperature flow. Electrical performance also improved with H2O-based high-k, suggesting that H2O-based ALD is the key process for III-V CMOS.
  • Exploring alternative high-k gate dielectrics for III-V, Ge and Si MOSFETs. High-field carrier mobility and MOSFET parameter characteristics were improved by atomic layer deposition (ALD) of a thin beryllium oxide layer to passivate the interface between the Si channel and high-k gate dielectric.

Non-Planar Devices

  • Studying FinFET Vt tuning. Both performance and the electrical properties of the gate stack were improved by an Al implantation, representing progress towards realizing multi threshold voltage FinFET device architectures for the 14 nm node and beyond.
  • Studying the impact of fin doping on high-k/midgap metal gate SOI FinFETs. Threshold voltage can be effectively modulated with doping in ~25 nm wide fins. For sub-10 nm fin widths, however, the active dopant atoms must be precisely placed inside the fins, which ion implantation cannot do. A conformal doping technique with perfect dose control, such as monolayer doping, was discussed which may be the solution for future planar and non-planar devices.
  • Evaluating the parasitic capacitance of planar FETs and double-gated (DG) FinFETs. Optimization with a fixed fin-to-height ratio significantly reduces parasitic capacitance, which renders DG FinFETs comparable to planar FETs. Fin width and height must be controlled in the DG FinFETs, otherwise the parasitic capacitance uniformity will degrade.
  • Investigating the impact of source/drain (S/D) activation anneal on GAA pFETs. Low temperature pFETs were fabricated and benchmarked against devices with a S/D activation anneal. When S/D is implanted before the gate spacer, the un-annealed devices exhibited higher peak transconductance and drain current but have a higher off-current than their annealed counterparts. Pre- and post-spacer S/D implant schemes were also explored.

Advanced Non-Volatile Memory

  • RRAM switching performance up to 1×108 cycles at low power and a 100x reduction of the high-resistance-state current was achieved by identification and utilization of key parameters for establishing superior control of the RRAM conductive filament formation.

More info: SEMATECH