MIT Research Team Speeds Chips with Internet Technology

Li-Shiuan Peh, an associate professor of electrical engineering and computer science at MIT, will present a paper at the 2012 Design Automation Conference in June. Peh and her colleagues will present a paper that summarizes ten years of research on networks on chip. In the paper, the researcher team established theoretical limits on the efficiency of packet-switched on-chip communication networks. In addition, they also presented measurements performed on a test chip in which they came very close to reaching several of those limits.

In order to keep increasing chips’ computational power, chipmakers are packing multiple cores (processing units) in chips. A typical chip might have six or eight cores, all communicating with each other over a single bundle of wires, called a bus. With a bus, however, only one pair of cores can talk at a time, which would be a serious limitation in chips with hundreds or even thousands of cores.

Peh wants cores to communicate the same way computers hooked to the Internet do: by bundling the information they transmit into “packets.” Each core would have its own router, which could send a packet down any of several paths, depending on the condition of the network as a whole.

In principle, multicore chips are faster than single-core chips because they can split up computational tasks and run them on several cores at once. Cores working on the same task will occasionally need to share data, but until recently, the core count on commercial chips has been low enough that a single bus has been able to handle the extra communication load. However, buses have a limit and are generally limited to about eight cores.

Ten-core chips found in high-end servers frequently add a second bus. Unfortunately that approach won’t work for chips with hundreds of cores. According to Peh, buses take up a lot of power because they are trying to drive long wires to eight or ten cores at the same time. In the type of network Peh is proposing, each core communicates only with the four cores closest to it.

Peh and her colleagues have developed two techniques of interest: virtual bypassing and low-swing signaling. Normally, a router inspects a packet addressing information before deciding which path to send it down. However, with virtual bypassing, each router sends an advance signal to the next, so that it can preset its switch, speeding the packet on with no additional computation. Based on test chips, virtual bypassing resulted in a very close approach to the maximum data-transmission rates predicted by theoretical analysis.

Digital data consists of ones and zeroes, which are transmitted over communications channels as high and low voltages. With low-swing signaling, the swing between the high and low voltages is decreased from one volt to 300 millivolts. With a combination of virtual bypassing and low-swing signaling, the researchers’ test chip consumed 38% less energy than previous packet-switched test chips. The test chip’s power consumption gets as close to the theoretical limit as its data transmission rate does.

More info: Massachusetts Institute of Technolog (MIT)