Synopsys Announces 3D-IC Initiative

Synopsys announced a 3D-IC initiative to accelerate the design of stacked multiple-die silicon systems. The initiative will use 3D-IC integration to meet the requirements of faster and smaller electronic products that consume less power. The Synopsys 3D-IC solution is available now in beta and is expected to be in production next quarter. As part of its 3D-IC initiative, Synopsys is working closely with IC design and manufacturing companies to deliver a comprehensive EDA solution, including enhanced versions of its IC implementation and circuit simulation products.

Synopsys’ 3D-IC initiative begins at the semiconductor device level. Multi-die stacks incorporate different materials, often bonded together, with varying coefficients of thermal expansion (CTE). Any temperature change causes material stress due to thermal mismatch, leading to silicon deformation and affecting transistor performance. In addition, TSVs, microbumps and other solder bumps produce a permanent stress in the zone around them. Synopsys’ Sentaurus Interconnect TCAD tool analyzes these effects and models the TSVs in the die stacks, enabling performance and reliability optimization. Semiconductor companies, such as foundries, use modeling results to create design rules specific to 3D-IC integration to ensure manufacturability and reliability.

3D-IC technology complements conventional transistor scaling to enable designers to achieve higher levels of integration by allowing multiple die to be stacked vertically, or in a side-by-side “2.5D” configuration on a silicon interposer. 3D-IC integration uses through-silicon via (TSV) technology, an emerging interconnection technology that will replace the traditional wire-bonding process in chip/wafer stacking. The use of TSVs can increase inter-die communication bandwidth, reduce form factor and lower power consumption of stacked multi-die systems.

Synopsys 3D-IC EDA Solution

  • DFTMAX Test Automation
    Design-for-test for stacked die and TSV
  • DesignWare STAR Memory System IP
    Integrated memory test, diagnostic and repair solution
  • IC Compiler
    Place-and-route support, including TSV, microbump, silicon interposer redistribution layer (RDL) and signal routing, power mesh creation and interconnect checks
  • StarRC Ultra Parasitic Extraction
    Support for TSV, microbump, interposer RDL and signal routing metal
  • HSPICE and CustomSim Circuit Simulation
    Multi-die interconnect analysis
  • PrimeRail
    IR-drop and EM analysis
  • IC Validator
    DRC for microbumps and TSVs, LVS connectivity checking between stacked die
  • Galaxy Custom Designer Implementation Solution
    Specialized custom edits to silicon interposer RDL, signal routing and power mesh
  • Sentaurus Interconnect
    Thermo-mechanical stress analysis to evaluate the impact of TSVs and microbumps used in multi-die stacks

More info: Synopsys 3D-IC Design Solutions