Synopsys and Arteris recently teamed on a joint analog and digital IP solution to implement the MIPI Alliance Low Latency Interface (LLI) 1.0 specification. The early integration and availability of the Arteris and Synopsys solution helps speed time to market for MIPI LLI adopters. Arteris and Synopsys’ joint MIPI LLI IP solution is available now for select early access customers. System hardware implementing the joint solution will be available in the second half of 2012.
The joint Synopsys-Arteris MIPI LLI solution features Arteris’ Flex LLI MIPI LLI digital controller IP and Synopsys’ DesignWare MIPI M-PHY IP. According to the two companies, the new MIPI LLI solution is the easiest and lowest risk path to adopting MIPI LLI. It eases adoption of the low latency chip-to-chip interface by providing high-quality IP that has been jointly validated and is ready for engineers to rapidly integrate into their SoCs
The new Synopsys-Arteris MIPI LLI solution offers high performance with low power consumption in a compact silicon footprint while providing interoperability with the MIPI standard. The joint solution gives system-on-chip (SoC) designers access to pre-tested and pre-optimized analog and digital MIPI-based IP that can reduce design cost and accelerate time to market.
The MIPI Alliance LLI specification enables high-bandwidth, low-latency inter-chip communication between two chips using a minimal number of SoC pins. The LLI specification utilizes the MIPI M-PHY physical layer, which also supports five other protocols including USB SSIC, JEDEC UFS, MIPI CSI-3, DSI-2 and DigRF v4. The round-trip latency of the LLI inter-chip connection is fast enough for a mobile phone modem to share an application processor’s memory while maintaining enough read throughput and low latency for cache refills. This enables phone manufacturers to remove the modem’s dedicated RAM chip from the phone’s bill of materials, MIPI Alliance estimates saving approximately $2 in cost per phone as well as significant printed circuit board (PCB) space that can be used for additional features or to create smaller or thinner devices.