Uniquify Solves Dynamic Variation Problems with Dynamic Self-Calibrating Logic

Uniquify has extended its patented self-calibrating logic (SCL) IP for double data rate (DDR) memory subsystems to solve dynamic variation problems during system operation. Dynamic Self-Calibrating Logic (DSCL) provides real-time calibration to accommodate dynamic variations in the system operating environment. Uniquify’s SCL and DSCL technologies now are included in all of their DDR memory controller IP offerings. This includes DDR1, DDR2, DDR3, DDR2/3, LPDDR1 and LPDDR2 phy and controller IP.

Dynamic Self-Calibrating Logic enables the memory subsystem timing calibration to be applied during system operation. This enhances system yield and maintains DDR memory system performance as temperature and supply voltages fluctuate during system operation. The new variation-aware DSCL technology is included with Uniquify’s high-performance DDR PHY/Controller subsystem IP.

Deep submicron SoC designs integrate DDR memory subsystems that operate at multi-gigahertz (GHz) clock rates. This results in read-write timing margins measured in picoseconds. As a result, designing the DDR memory subsystem to accommodate variations in system-level timing parameters during read and write cycles is challenging. Dealing with critical timing requirements can require exhaustive rounds of incremental system-level parameter tuning, yet the resulting silicon often fails to deliver optimal system yield in volume production.

Uniquify’s initial SCL technology solves this problem by performing an automatic self-calibration at system power-up for optimal DDR interface timing. DDR memory subsystems implemented with SCL exhibit higher yield due to their ability to automatically adapt critical timing characteristics for a wide range of system-level design choices and for variations in both the SoC and DDR memory processes.

The new DSCL technology builds on SCL by extending the precise timing calibration to execute dynamically during system operation, not just at system power on. During system operation, temperature and supply voltages vary over time, degrading DDR memory performance and, if severe enough, can cause intermittent memory subsystem failure.

DSCL automatically re-calibrates the critical DDR memory interface timing at user-specified intervals during system operation. It is typically set to operate during periods of lower activity for the smallest impact on system throughput. The DSCL calibration is fast and the hardware required to support the addition of DSCL is minimal.

More info: Uniquify