Imec released an early version of a process development kit for 14nm logic chips. The 14nm PDK was developed as part of imec’s INSITE program, and together with all the partners involved in this collaborative affiliation program. The process development kit will be made available to imec’s partners, and will include incremental updates. In addition, imec and its partners are developing a 14nm test chip to be released in the 2nd half of 2012 using this PDK.
The process development kit is the world’s first to address the 14nm technology node. It targets the introduction of a number of new key technologies. The main example is the use of FinFET transistors, which have a larger drive per unit footprint and higher performance at low supply voltages compared to the traditional planar technologies. Evolutions of this PDK will gradually also introduce the use of high-mobility channel materials. The PDK includes elements of both immersion and EUV lithography. This will open the way for a gradual transition from 193nm immersion to EUV lithography.
The 14nm PDK contains all elements for design assessment of the 14nm node through device compact models, parasitic extraction, design rules, parameterized cells (pcells), and basic logic cells. Starting from the PDK, imec and its partners are now designing a first test chip. The chip is planned for the 2nd half of 2012. It will allow testing the device-, interconnect-, process- and litho assumptions, as well as performance and power of circuits implemented at the tight area budgets of the 14nm node.
More info: imec