Imec and Renesas Electronics teamed together to develop a successive-approximation register analog to digital converter. The new ADC is an ultra-low power (1.7mWatt) high resolution (11b) fully-dynamic, two-step interleaved pipelined SAR ADC with a record power efficiency of 10fJoule per conversion step at a sampling speed as high as 250MSamples/s. The SAR ADC is ideal for wireless receivers for next-generation high-bandwidth standards such as LTE-advanced and the emerging generation of Wi-Fi (IEEE802.11ac).
The new SAR ADC architecture is an answer to the need for much faster low-power ADCs with small form factor. The increase in the speed and sampling frequency of the SAR ADC are both an order of magnitude better than state-of-the art available ADC IP blocks.
This result is obtained with a new converter architecture based on prior ADC designs from imec. The design uses completely dynamic circuits, such that the power consumption scales linearly with the sampling frequency, and is implemented with a maximum amount of digital content, leaving the comparator as the only analog building block.
The ADC prototype has been manufactured in 40nm CMOS with a core chip area of 0.066mm2. Measurements show a DNL and INL of respectively 0.8/-0.5 and 1.1/-1.5 LSB. The dynamic performance is characterized by 62dB SNDR (10.0 ENOB) at 10MSamples/s, which is maintained up to 9.5 ENOB level for a sampling speed of up to 250MSamples/s. The power consumption is 6.9pJoule per conversion (70µWatt at 10MSamples/s, 1.7mWatt at 250MSamples/s), resulting in a spectacular energy efficiency of 7 to 10fJoule per conversion-step.