Imec Develops Reconfigurable Digital Receiver with Record Area Efficiency

Imec announced it has developed a reconfigurable receiver for highly diversified digital video broadcasting standards (DVB-T, ISDB-T and ATSC). The reconfigurable receiver was developed by using algorithm-architecture co-optimization of imec’s ADRES reconfigurable processor. ADRES is short for architecture for dynamically reconfigurable embedded systems.

The instantiation of imec’s ADRES reconfigurable processor was optimized by combining innovative algorithms (highly parallel implementation, software optimizations) with architecture improvements (optimized intrinsics, exploration towards leaner instance). The optimizations resulted in a smaller silicon area than the ASIC counterparts of the considered broadcasting standards. In addition to area efficiency, imec’s baseband processor is highly flexible. It supports Digital TV standards (ATSC, ISDB-T, DVB-T,…) and also other wireless communication standards: both an IEEE 802.11n inner receiver and a cat-4 LTE receiver can run real time on the same architecture.

The optimizations were realized as a result of Panasonic’s partnership in imec’s green radio research program.

Digital broadcasting has gained a lot of interest. However, its deployment in products can be hampered by the many different regional standards that have been adopted world-wide. Due to the ultimate programmability, software-defined radio (SDR) solutions are becoming more and more attractive. Reconfigurable processor-based implementations reduce design costs and speed time-to-market. However, SDR baseband solutions are traditionally reported to come with an area penalty when compared to ASIC counterparts. As area efficiency is one of the most important factors that determine the final cost of commercial chipsets, competitive area efficiency is crucial for SDR baseband solutions.

More info: imec