The preliminary DFI 3.0 specification was released by the DDR PHY Interface Technical Group today. The DDR PHY interface is the pervasive industry specification that defines an interface protocol between DDR memory controllers and PHYs. DFI 3.0 specification enables the development of chips to support the emerging DDR4 memory standard.
DFI 3.0 Specification
- Defines methods for interfacing to DDR4 devices
- Proposed data rates up to 3.2 Gbits/second per pin
- Over 50% faster than the current DDR3 standard
- Extends the low-power interface that was introduced with DFI 2.1
- Accounts for frequency and power challenges at high speeds
- Helps ensure exceptional performance in systems using DDR4 memory
The DFI 3.0 specification is the result of collaborative work between the DFI Technical Group members, which includes ARM, Cadence Design Systems, Intel, LSI, Samsung Electronics, ST-Ericsson and Synopsys. The DFI interface is supported by major DDR IP suppliers, and is in use by hundreds of companies. The preliminary DFI 3.0 specification is available now for download.
More info: DFI Technical Group