Imec and Cadence Automated Test Solution for 3D Stacked ICs

Cadence Design Systems and imec teamed together to develop technology for testing 3D stacked ICs (3D-ICs). Their automated test solution makes it easier to test 3D-ICs with through-silicon via (TSV) functionality and helps ensure that the stacked system will work as intended. The solution includes design-for-test (DFT) and automatic test pattern generation (ATPG) technology.

Automated Solution for Testing 3D Stacked ICs Highlights

  • Automated test solution for 3D stacked ICs
  • Features design-for-test and automatic test pattern generation technology
  • Makes it easier to test 3D-ICs with through-silicon via functionality
  • Helps ensure stacked systems will work as intended
  • Imec extended DFT architecture for conventional (2D) ICs with patent-pending features
  • 3D DFT architecture is based on the concept of die-level test wrappers
  • Enables testing of chips with TSVs and micro-bumps both before (pre-bond test), during (mid-bond test), after (post-bond test) stacking, and after packaging
  • Inserts DFT structures with minimal area overhead
  • ATPG method helps drive towards zero manufacturing defects on the TSVs
  • Reduces risk and promotes cost-effective fabrication of these chips
  • Design flow automation for adding 3D-enhanced IEEE 1500-based die wrappers to existing chip designs
  • Enhanced IEEE 1500 wrapper insertion support in the Cadence Encounter RTL Compiler synthesis product
  • 3D DFT structures can be implemented with negligible area costs (about 0.2%)

More info: imec | Cadence Design Systems