Principles of VLSI RTL Design: A Practical Guide

A new RTL design textbook was published recently by Springer Science+Business Media. The title of the book is, Principles of VLSI RTL Design: A Practical Guide. The book was written by Sanjay Churiwala and Sapan Garg. Topics of the book include reliable RTL construction, clock domain crossings and clock synchronization, design for test and testability, power consumption, static timing analysis, timing exception handling and routing congestion.

The 220-page book is based on the authors’ experiences while working at Atrenta’s Noida, India R&D center. The text book is ideal for RTL designers and provides useful information on design practices and how they affect downstream implementation tasks.

Since register transfer level (RTL) design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains the impact of design decisions taken that may give rise later in the product lifecycle to issues related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc., all which are a function of the way the RTL was originally written. Readers will benefit from a highly practical approach to the fundamentals of these topics, and will be given clear guidance regarding necessary safeguards to observe during RTL design.

In the process of integrated circuit design, front-end activities start with a register transfer level (RTL) description, of the functionality desired from the IC. During subsequent steps in the design flow, issues may arise related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc. which are a function of the way the RTL was originally written.

As a result, RTL designers need to take care of many aspects which can have impact on later steps in the design process. Since RTL design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains those various aspects, their significance, what caution needs to be taken during RTL design and why.? Readers will benefit from a highly practical approach to the fundamentals of uncertainties around functionality, clock domain crossing and clock synchronization, design for test and testability, power consumption, static timing analysis, timing exception handling, and routing congestion.

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