Design Flow for Heterogeneous 3D Stacked ICs

Atrenta and imec teamed together to develop an advanced planning and partitioning design flow for heterogeneous 3D stacked ICs. 3D stacked ICs feature reduced footprint with shorter and faster interconnects, increased system integration at a lower cost, and higher modularity and reuse. 3D stacked ICs are ideal for mobile and high-performance applications, imagers, stacked DRAM, and solid-state drives.

Exploration Flows for 3D ICs Highlights

  • Planning and partitioning design flow for heterogeneous 3D stacked ICs
  • Minimizes the number of design iterations, facilitating a cost- and time-effective search of the solution space
  • Reduced footprint with shorter and faster interconnects, increased system integration at a lower cost, and higher modularity and reuse
  • Compact thermal and mechanical models for rapid generation of heat dissipation and mechanical stress maps developed by imec
  • Stress models have been validated with real 3D DRAM-on-logic packaged devices
  • Different scenarios can be assessed quickly and the best option can be selected in advance of a full design implementation
  • Stress models can be used with Atrenta’s SpyGlass Physical 3D prototyping tool
  • Target applications include: products for mobile and high-performance applications, imagers, stacked DRAM, and solid-state drives

More info: Imec | Atrenta