Patent Office Approves Two Texas Memory Systems Patents

The U.S. Patent Office granted two patents to Texas Memory Systems. The patents cover techniques to increase reliability within their systems and for the Flash media used with their devices. The two patents approved are: (1) Patent No. 7,928,791 – Method and apparatus for clock calibration in a clocked digital device and (2) Patent No. 7,818,525 – Efficient reduction of read disturb errors in NAND Flash memory.

Method and Apparatus for Clock Calibration in a Clocked Digital Device Patent

  • Increases the reliability of the RamSan systems
  • Provides predictable performance for a wide range of integrated circuit devices, including Field Programmable Gate Arrays (FPGA) and Application-specified integrated circuits (ASIC)
  • Fine tunes calibration of the timing requirements on every clock cycle to increase the reliability of the system
  • Relies solely on the clock signal itself to establish stable input and output characteristics across wide variations in process, voltage and temperature

Efficient Reduction of Read Disturb Errors in NAND Flash Memory Patent

  • Relates to the way Texas Memory Systems prevents read disturb errors
  • Technique initiates an action that moves the data once the number of reads performed on a particular section of data has reached a specified count threshold
  • Removes the built up voltage and returns the data to an uncompromised state
  • Ensures reliability of the data stored on a Texas Memory Systems’ devices

More info: Texas Memory Systems