Mentor Graphics Reveals 3D-IC Strategy

Mentor Graphics revealed its 3D-IC strategy for designing, verifying, manufacturing and testing integrated circuit products using multi-die vertical stacking technology. Mentor also announced their 3D-IC testing solution, which includes multiple components of the Tessent design-for-test product line for integrated multi-die hierarchical scan and built-in self-test (BIST) methodologies. 3D-IC is an alternative to traditional scaling for achieving advances in performance, reduced power consumption, cost reduction, and increased functionality in a small package.

Mentor 3D-IC Strategy Highlights

  • Addresses both 2.5 and full 3D test requirements
  • Tessent results in high test quality while reducing development time and manufacturing test costs
  • Creates both highly compressed deterministic scan patterns, and on-chip generated random patterns
  • High coverage while minimizing test time
  • Seamless infrastructure for testing 3D structures including processor cores, logic, memory and high-speed I/O
  • Can reuse die-level ATPG and BIST tests at the package level
  • Enables the creation of a hierarchical DFT architecture that is based on the IEEE 1149.1 standard
  • Enables die-level patterns to be routed through multiple die after packaging
  • Scan patterns can target TSV interconnects by accessing scan chains on multiple die
  • Die-targeted ATPG patterns can be retargeted to the package level with automatic pattern re-timing
  • Ability to reuse patterns and reduce test development time
  • At-speed testing of stacked memory die with support for all popular DRAM protocols
  • Memory parameters (address size, waveforms) and test algorithms can be programmed post-silicon
  • Enables memory BIST controllers in a logic die to handle a variety of memory die stacked on top for different product variations
  • Supports at-speed testing of memory buses, which covers both bond wires and TSV interconnects
  • A shared-bus capability enables test of multiple memory die on the same interconnect

More info: Mentor Graphics