SEMATECH Develops Bond Process for 3D IC Applications

SEMATECH developed a die-to-wafer interconnect process using a die-tacking and collective-bonding approach on a 300mm wafer platform for 3D-IC applications. Composite wafers containing a 50µm thin through-silicon-via (TSV) wafer attached to a supporting handle wafer were populated with dice using a short, low-temperature tacking process. SEMATECH presented their wafer bonding research at the Device Packaging Conference (DPC).

According to SEMATECH, wafer-to-wafer (WtW) bonding is a key enabling process step for 3D interconnection of wafers through stacking. The International Technology Roadmap for Semiconductors (ITRS) roadmap for high density, intermediate level, TSVs specifies diameters of 0.8 to 4.0µm in 2012 and beyond. SEMATECH’s breakthrough results in a faster method of die-to-wafer integration needed for the advancement of heterogeneous 3D-IC. Their implementation approach is critical to the integration and process development that will make 3D TSVs commercially viable.

3D ICs will play an important role in the semiconductor industry, given their potential to alleviate scaling limitations, increase performance and functionality, and reduce cost. In this emerging field, new and improved technologies and integration schemes will be necessary to realize 3D’s potential as a manufacturable and affordable path to sustaining semiconductor productivity growth.

More info: SEMATECH