Accellera Universal Verification Methodology Standard

Accellera has approved version 1.0 of their Universal Verification Methodology (UVM) standard. UVM 1.0 is available as a Class Reference Manual. The UVM standard establishes a methodology to improve design and verification efficiency, verification data portability, and tool and VIP interoperability. The UVM Class Reference Manual is available for free. It includes an open-source SystemVerilog base class library implementation and a User Guide. Accellera is an electronics industry organization focused on the creation and adoption of Electronic Design Automation (EDA) standards and Intellectual Property (IP) standards.

Accellera Universal Verification Methodology (UVM) standard run time phases

UVM 1.0 Standard Highlights

  • Methodology to improve design and verification efficiency, verification data portability, and tool and VIP interoperability
  • Leverages features from the baseline UVM 1.0 Early Adopter (EA) release, which is a direct derivative of the Open Verification Methodology (OVM)
  • UVM 1.0 fully qualifies the baseline features, corrects most of the known bugs and implements enhancement requests
  • Phasing mechanism
  • Register Package (derived from Verification Methodology Manual (VMM) technology)
  • Supports Open SystemC Initiative’s (OSCI) Transaction Level Modeling-2.0 (TLM-2.0)
  • Upgraded configuration mechanism (or Resource Manager)
  • Standardized command line interface
  • Includes callbacks, message catching and functionality in the objection mechanism to manage end of test
  • Available as a UVM Class Reference Manual (free)
  • Includes an open-source SystemVerilog base class library implementation and a User Guide
  • Developed by Accellera’s Verification IP (VIP) Technical Subcommittee (TSC)

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