SYSGO ELinOS Supports Cavium Networks OCTEON Plus MIPS64 Processors
SYSGO, leading supplier of software solutions for the world’s most demanding safety and security applications, announces the availability in its ELinOS product of support for Cavium Networks’s OCTEON Plus family. The new SYSGO support package combines the high performance at minimal power levels multi-core platform with industrial grade Linux for rapid development of reliable long-lived applications.
MoSys Forms GigaChip Alliance for Serial Chip-to-Chip Communications
MoSys, Inc. (NASDAQ: MOSY), a leading provider of differentiated high-density memory and high-speed interface (I/O) intellectual property (IP), announced the launch of the GigaChip[tm] Alliance, an ecosystem of semiconductor device suppliers in support of the GigaChip[tm] Interface. The founding alliance participants are: MoSys, Altera Corporation and NetLogic Microsystems. The GigaChip Interface is a board-level, open, CEI-11 compatible interface developed to enable highly efficient serial chip-to-chip communications in next generation high-performance networking, computing and storage systems. In February 2010, MoSys announced the GigaChip Interface as a key element of the new Bandwidth Engine family of ICs. Through the GigaChip Alliance, participating companies will collaborate on expanding the GigaChip Interface for high-speed serial chip-to-chip applications and developing industry-wide open interoperability standards and tools to accelerate the adoption of serial chip-to-chip based system designs.
Cadence, ARM Optimize System Realization Solution for Processors
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced a broadening of its existing collaboration with ARM to develop an optimized System Realization solution for ARM processors that will enable an end-to-end flow including a full set of interoperable tools, ARM® processor and physical IP, services and methodology from embedded Linux to GDSII. To accelerate adoption of this solution, Cadence will provide a full complement of tutorials and education materials including two methodology reference books and extend their ecosystem of service, methodology and training providers.
Cadence, Fujitsu Team on Chip Package Board Co-Design Solution
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced that, with the assistance of Fujitsu Semiconductor Limited and Fujitsu VLSI Limited (hereafter collectively called Fujitsu), Cadence has developed a standardized die model that provides ASIC and microcontroller (MCU) designers with a comprehensive chip-package-board co-design solution.
RFEL Extends Wideband Digital Down Converter IP Core to 1 GHz
RF Engines Limited (RFEL) has extended the range of its Digital Down Converter (DDC) technology so that it can now process up to 1 GHz of bandwidth (2Gsps ADC rate) input and provide a narrower band output. This technology can operate with fixed frequencies and bandwidths or be fully flexible as required. One of the main application areas is for Electronic Surveillance in military digital receivers, where this approach enables a desired signal band to be extracted from a wide slice of the spectrum in order that further analysis of the signal content can be carried out.
Actel Qualifies RT ProASIC3 FPGA Family for Space Flight Systems
Reaffirming its leadership in the space market, Actel Corporation (Nasdaq: ACTL) announced the first fully qualified flash based FPGAs for space flight applications. Actel’s RT ProASIC®3 family successfully passed the extensive testing required for MIL-STD-883 Class B qualification. Building on its 17 year heritage and leadership of providing antifuse FPGAs for system critical applications, Actel ushers in a new paradigm in the space market with the qualification of its flash-based RT ProASIC3 devices.
Actel RTAX-DSP FPGA Devices Qualify for MIL-STD-883 Class B
Actel Corporation (Nasdaq: ACTL) announced that its radiation-tolerant RTAX-DSP FPGAs have completed qualification in accordance with the military and aerospace industry standard MIL-STD-883 Class B specification. This qualification expands Actel’s support of high-speed signal processing applications for space payloads and exemplifies its ongoing innovation and commitment to serve designers of spaceflight systems.
Lattice Offers 90+ Reference Designs for MachXO, ispMACH 4000ZE PLDs
Lattice Semiconductor Corporation (NASDAQ: LSCC) announced that it has released more than 90 reference designs optimized for the MachXO[tm] and ispMACH® 4000ZE PLDs. Reference designs enable the quick and efficient design and deployment of commonly used functions such as general purpose I/O expander, I2C bus master / slave, LCD controller and SD Flash controller, as well as other interfaces, in a variety of markets including consumer, communications, computing, industrial and medical. The reference designs, coupled with complete documentation and design source code, are fully customizable and enable designers to reduce design time, boost productivity and accelerate time-to-market.
STMicroelectronics Standardizes on Cadence QRC Extraction
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced that STMicroelectronics, a global leader in integrated circuits for communications, consumer, computer, automotive and industrial applications, has standardized on Cadence® QRC Extraction for their 40-nanometer custom/analog designs. A key component of the Cadence digital and analog/mixed signal design flow, QRC Extraction enables faster turnaround time, scalability through its multi-core backplane, increased accuracy to silicon and capabilities to address the needs for advanced layout parasitic extraction in leading-edge technology node design.
ASSET InterTech, IPextreme Team on IEEE 1149.7 Test Solution
ASSET® InterTech, Inc., the leading supplier of open tools for embedded instrumentation, will integrate test adapter intellectual property (IP) from IPextreme into its ScanWorks® platform for embedded instruments to enable chip and circuit board tests under the new IEEE 1149.7 reduced-pin boundary scan standard. “IPextreme leads the market with the industry’s first IEEE 1149.7 synthesizable IP,” said Pierre Xavier-Thomas, vice president of engineering, IPextreme. “We are excited about working with ASSET to accelerate the availability of IEEE 1149.7 tools in the marketplace. This will enlarge the IEEE 1149.7 ecosystem and benefit end users.”
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