Azuro, Inc., the provider of advanced clock and timing optimization tools for digital chip design, announced that TSMC has adopted its Rubix[tm] clock concurrent optimization capability for hardening of embedded CPU cores. “With Rubix, Azuro continues its track record of strong technology innovation to help close the design productivity gap,” said S. T. Juang, senior director of design infrastructure marketing at TSMC. “Rubix increases clock frequency and reduces leakage power on our hardened CPU cores. And it does this without any change in sign-off methodology.”
At advanced process nodes, rising on-chip-variation and rising clock latencies are causing design timing to diverge after clock tree synthesis, even if tight skews are achieved. Clock concurrent optimization is a new approach to clock tree synthesis (CTS) which builds clocks directly to deliver the best timing and power rather than simply to deliver tight skews. Since the clocks are also built concurrently with logic sizing and placement, efficient global trade-offs can be made between fixing timing problems with clock skew and fixing timing problems with logic sizing or placement.
“Azuro and TSMC share a common belief that at advanced process nodes there is currently a gap between what the silicon can offer and what design flows can deliver,” said Paul Cunningham, CEO of Azuro. “Replacing clock tree synthesis with clock concurrent optimization is a vital change our industry needs to make to close the productivity gap at advanced process nodes. We are delighted that TSMC has adopted Rubix for hardening of their embedded CPU cores.”
For more information on clock concurrent optimization, see the white paper at www.azuro.com/rubix/white-paper.html
Rubix is a unified placement, sizing, and useful skew-based clock tree synthesis tool for digital standard cell-based chip designs. It increases clock frequencies by up to 25%, reduces leakage power by up to 30%, and accelerates timing closure in the back end of the design flow by up to two months.
Azuro is an electronic design automation company supplying software tools for use designing digital semiconductor chips. The company’s unique clock and timing optimization technologies make chips faster, reduce chip power and dramatically accelerate chip time to market. Founded in 2002, the company is headquartered in Santa Clara, CA with R&D in Cambridge, UK, and is privately held.