Calibre Automatic Waivers Speed SoC Verification for TSMC

Mentor Graphics Corporation (NASDAQ: MENT) announced that Taiwan Semiconductor Manufacturing Corporation (TSMC) has completed technical validation of the Calibre® Automatic Waivers solution and is in the process of adopting it to speed verification of large SoCs. The new facility allows TSMC, their IP ecosystem, and customers to attach design rule checking (DRC) waivers to their IP datasets so that waived violations will not appear during verification runs. This cuts down on DRC debugging as well as unnecessary interactions between the designer and TSMC for previously waived IP, reducing the time to tapeout. Customers have seen an order of magnitude reduction in time required to review false (waived) DRC violations in large SoC designs after adoption of the Calibre Automatic Waivers flow. TSMC is planning to use Calibre Automatic Waivers with TSMC-developed IP.

According to ST Juang, senior director of Design Infrastructure Marketing at TSMC, “This solution allows users to identify and suppress DRC error results in IP if they meet appropriate criteria defined by the foundry. This saves our customers significant debug time, without the risk of accidentally waiving true errors. Unlike previous approaches, the Calibre solution accurately accounts for waivers across cell hierarchies without placing a significant burden on the user.”

For example, users at MediaTek Inc. find it is common to have hundreds or thousands of DRC violations in IP at the chip level resulting from design rules that have previously been reviewed and waived by the foundry. The company reports that previously a significant amount of time was spent unnecessarily reviewing each waiver violation simply because there was no efficient way to transfer the waiver information along with the IP when it is incorporated into a design. The Calibre Automatic Waivers solution is now being used by MediaTek to efficiently capturing waivers at the time they are approved, allowing waiver violations to be automatically and accurately removed from DRC results, which significantly reduces debug time.

“Communicating waivers between the design and foundry teams can be a big time sink, and it’s easy to inadvertently lose information in the process,” said Mark Judiscak, CAD Director at Microchip Technology Inc. “By incorporating waiver information directly into the IP datasets, it becomes available wherever the IP is used. Not only does the designer save debug time that is typically wasted reviewing false DRC violations, but the foundry team also has immediate visibility into exactly which results were waived for a given DRC rule. This greatly expedites communication and resolution of issues.”

“Our customers have been asking for a solution to this problem, which is growing as SOC designers make more and more use of external IP in order to add more functionality and speed their time to market,” said Joseph Sawicki, vice president and general manager for the design-to-silicon division at Mentor Graphics. “This productivity enhancer is one of the many ways we continue to add value to maintain Calibre’s position as the industry’s most popular physical verification platform.”

About Waivers in IC Design
Typically, a foundry qualifies IP that its customers can use in IC designs to be manufactured at a specific process node. During qualification of the IP, any violations to standard design rules are reviewed, and if it is determined that the structures can be manufactured, certain checks are ‘waived’ for those specific structures and the particular process. The difficulty is in later tracking the waivers when IP is inserted into an IC design in many places and at multiple levels of the design hierarchy. Often, the waived DRC violations re-emerge and a lot of time is wasted cross-checking each violation to determine if it is a waived error, or a real error.

With the Calibre Automatic Waivers solution, waivers approved by the foundry are included as part of the IP files prior to use by chip designers. The Automatic Waivers facility records the description of waivers on a single reserved GDSII or Oasis layer and automatically associates each waiver with its appropriate check at runtime. Error results associated with a waiver are suppressed if they meet appropriate criteria defined by the foundry. With this new feature, all previously waived results are properly eliminated regardless of the hierarchical location of the feature. When designers run the Calibre tools, they simply use a command line option to automatically identify and remove waived DRC errors. The Calibre tools also explicitly report the waived errors to create an audit trail. The unique benefit of the Calibre Automatic Waivers solution is that it works seamlessly across cell hierarchies without additional effort on the part of the designer.

About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,425 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.

Mentor Graphics and Calibre are registered trademarks and Olympus-SoC is a trademark of Mentor Graphics Corporation.