TSMC, Mentor Graphics, Synopsys Donate iDRC Specification to Si2
Silicon Integration Initiative (Si2) announced that TSMC has donated iDRC, a vendor-neutral language for describing IC design rules, for consideration as an open industry standard. iDRC is an open specification that makes it possible for TSMC and its customers to create physical verification design kits that allow easier support of physical verification products from different EDA vendors. TSMC has donated the iDRC specification to Si2, the organization of industry-leading silicon systems and EDA companies, on behalf of TSMC and its co-development partners, Mentor Graphics, and Synopsys.
Calibre nmLVS Supports iLVS Interoperable Rule Specification
Mentor Graphics Corporation (NASDAQ: MENT) announced that the Calibre® nmLVS product now provides comprehensive support for the iLVS interoperable rule specification used by TSMC for new design kits. This allows customers to define and customize complex IC design rules, as needed, while maintaining compliance with TSMC specifications and allowing seamless adoption of EDA vendor performance optimizations.
TSMC Rolls Out .18-Micron Automotive Embedded Flash IP
Taiwan Semiconductor Manufacturing Company, Ltd. (TWSE: 2330, NYSE: TSM) announced the 0.18-micron automotive Embedded Flash IP as its second generation Embedded Flash IP that passed AEC-Q100 product qualification requirements for a wide range of automotive applications. TSMC’s 0.18-micron automotive Embedded Flash IP macro features 27 percent area reduction compared to an equivalent 0.25-micron Embedded Flash IP.
UMC Qualifies Silicon Frontline Fast 3D Extraction Software
Silicon Frontline Technology, Inc. (SFT) announced that its 3D extraction software for post-layout verification F3D (Fast 3D) has been qualified by United Microelectronics Corporation (NYSE: UMC, TSE: 2303) (“UMC”), a leading global semiconductor foundry, as the reference field solver for parasitic extraction. UMC verified F3D’s accuracy through extensive comparison with internal benchmarks.
CEITEC Selects Tools from Cadence Design Systems
CEITEC S.A. announced that the company has formed an alliance with Cadence® Design Systems, Inc. (NASDAQ: CDNS), the global leader in EDA360, under which the Brazilian chipmaker will use a broad selection of Cadence electronic design automation (EDA) products and services to design semiconductors.
Universal Display Develops All-Phosphorescent AMOLED Architecture
Universal Display Corporation (NASDAQ: PANL), enabling energy-efficient displays and lighting with its UniversalPHOLED(TM) technology and materials, will announce an all-phosphorescent AMOLED display architecture that uses a novel four-color sub-pixel design. The new pixel format adds a light blue sub-pixel to the conventional red-green-blue (RGB) configuration. The introduction of a light blue sub-pixel can significantly extend the operational lifetime of an OLED display and reduce the display’s power consumption by as much as 33%, as compared to an RGB OLED display using a fluorescent blue sub-pixel.
Berkeley Design Automation Debuts Multi-Core Parallel Operating Mode
Berkeley Design Automation, Inc., provider of the Analog FastSPICE[TM] unified circuit verification platform (AFS Platform), announced the AFS Multi-Core Parallel operating mode (AFS MCP). AFS MCP automatically runs corners, sweeps, and Monte Carlo iterations in parallel on separate cores on up to 8-core shared-memory systems. The result is 25x to more than 50x higher performance than traditional SPICE on single-core systems with identical accuracy and no use model changes.
ARM Selects Magma SiliconSmart Characterization, Modeling Software
Magma Design Automation Inc. (Nasdaq: LAVA), a provider of chip design software, announced that ARM (LSE: ARM; Nasdaq: ARMHY) has successfully utilized Magma’s SiliconSmart characterization and modeling software suite to enhance and expand ARM’s production characterization system for Physical IP products. This fast, accurate and easy-to-use characterization system will assist ARM in delivering standard cell and I/O libraries.
Duolog Socrates Chip Integration Hub Supports Cadence EDA360
Duolog Technologies, the award-winning developer of IP and SoC integration products, announced that its Socrates Chip Integration Hub supports key elements of the EDA360 vision recently unveiled by Cadence. EDA360 cites the growing need for an “Open Integration Platform” to improve productivity and profitability through integration of hardware and software development activities, accelerated software development, improved IP integration, IP reuse and open standards. The Socrates Chip Integration Hub is a standards-based IP integration platform that addresses these issues by raising the level of abstraction at which IP is handled, centralizing and synchronizing design and IP metadata and automating many of the steps involved in the creation of virtual prototypes, FPGAs and SoCs.
Imperas Debuts Embedded Software Flow with Mentor Nucleus RTOS, EDGE
Imperas announced a flow with Mentor Graphics Corporation (Nasdaq: MENT) focused on enabling more productive and higher quality embedded software development with the Mentor Graphics® Nucleus Real-Time Operating System (RTOS) and the Mentor Embedded[TM] software tools. With firmware and application software development taking the majority of the resources for developing embedded, creating new flows for embedded software is increasingly important. The Imperas flow with Mentor Graphics Embedded Software Division (ESD) tools, including the Mentor Nucleus RTOS and EDGE products, makes it easier to use the Open Virtual Platforms (OVP) open source models for the development of embedded systems.
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