Azuro, Inc., a leading provider of advanced clock tree synthesis and timing optimization tools for digital chip design, announced that Azuro has become a member of the Cadence Design Systems Connections® program. Azuro has also been a long standing member of the Power Forward Initiative and is developing interoperability software that takes advantage of the Common Power Format (CPF) to link Azuro’s PowerCentric[tm] clock tree synthesis to CPF-enabled low power design flows.
“PowerCentric is used within Cadence-based design flows at some of the world’s biggest chip companies,” said Paul Cunningham, CEO and co-founder of Azuro. “CPF is gaining significant traction within our user base and we applaud Cadence’s leading role in making CPF such a practical success.”
Azuro plans to ship support for CPF in PowerCentric in Q2 this year.
“We are committed to collaborating with the ecosystem in support of our customers,” said Pankaj Mayor, group director of business development at Cadence. “We’re pleased to see Azuro actively participating in both the Cadence Connections program and the Power Forward Initiative.”
PowerCentric is a clock tree synthesis tool for digital standard cell based chip designs. It reduces chip power by up to 20% and dramatically increases designer productivity on designs with complex clock networks.
Azuro is an electronic design automation company supplying software tools for use designing digital semiconductor chips. The company’s unique clock tree synthesis and timing optimization technologies make chips faster, reduce chip power and dramatically accelerate chip time to market. Founded in 2002, the company is headquartered in Santa Clara, CA with R&D in Cambridge, UK, and is privately held.