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Archive for March 2010

OMG, Wireless Innovation Forum Offer Membership Discounts

Posted by Ken Cheung in Models, Simulations,Wireless on Wednesday, March 31, 2010

Leaders of computer industry standards organization OMG[tm] and reconfigurable radio technologies industry association The Wireless Innovation Forum met recently at a joint meeting of the Wireless Innovation Forum and JTRS JPEO, to discuss ways they can better serve the members of both organizations. Key outputs resulting from this meeting include a plan to develop a whitepaper highlighting the process followed and success achieved in the joint development of the “PIM and PSM for Smart Antenna” specification, and discounts on first-year membership for members of each organization to join the other to simplify and support collaborative development in the future.

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Rohde & Schwarz Adopts Cadence Virtuoso Accelerated Parallel Simulator

Posted by Ken Cheung in Models, Simulations on Wednesday, March 31, 2010

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that Rohde & Schwarz, a market leader in complex RF test and measurement products, improved the quality and functionality of its complex RF integrated circuits (RFICs) through an increased simulation depth using Cadence® Virtuoso® Accelerated Parallel Simulator (APS).

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ITTIA DB SQL Out Performs SQLite Database on ARM Device

Posted by Ken Cheung in Database on Tuesday, March 30, 2010

ITTIA, a global supplier of embedded lightweight relational database software, demonstrates its database benchmark leadership to application developers of embedded systems and devices, with exceptional results. On an ARM device, ITTIA DB SQL surpasses SQLite, an open source database, in three critical areas: insert, select, and update. ITTIA’s flagship product, ITTIA DB SQL, is an industry-leading RDBMS that provides performance and reliability in embedded environments, from embedded Linux and Windows Mobile to desktop workstations.

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Infineon Technologies Selects Synopsys Galaxy Implementation Platform

Posted by Ken Cheung in EDA Tools on Tuesday, March 30, 2010

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that the Galaxy[tm] Implementation Platform has helped Infineon Technologies AG (NYSE: IFX) achieve first-pass silicon success of the 40-nanometer (nm) baseband processor for its X-GOLD[tm] 626 3G wireless analog and digital system-in-package (SIP). Infineon utilized the Galaxy platform’s powerful implementation flow to optimize the chip’s multiple functional modes with multi-corner/multi-mode (MCMM) technology, taking advantage of the links between Synopsys’ Design Compiler® RTL synthesis solution and IC Compiler placement and routing. The Galaxy platform’s extensive support for low power and hierarchical design techniques, coupled with its signoff capabilities, was essential to achieve Infineon’s tight schedule and high-performance, low power and area goals. As a result, Infineon met its design targets and taped out the baseband processor for the X-GOLD 626 wireless product ahead of schedule.

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Vishay Offers IHLP Inductors in 6767 Case Size

Posted by Ken Cheung in Components on Tuesday, March 30, 2010

Vishay Intertechnology, Inc. (NYSE: VSH) launched a new IHLP® low-profile, high-current inductor in the 6767 case size. Featuring an ultra-low 4.0-mm profile, the IHLP-6767DZ-01 offers a high maximum frequency, saturation currents up to 92 A, and standard inductance values from 0.22 µH through 10.0 µH.

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MIPS Technologies, Virage Logic Optimize Embedded Memory IP

Posted by Ken Cheung in IP Cores on Monday, March 29, 2010

MIPS Technologies (Nasdaq: MIPS), a leading provider of industry-standard processor architectures and cores for digital consumer, home networking, wireless, communications and business applications, and Virage Logic Corporation (Nasdaq: VIRL), the semiconductor industry’s trusted IP partner, announced they are teaming to offer optimized embedded memory IP for joint customers. With SRAM memory instances from the Virage Logic ASAP[TM] 90nm and SiWare[TM] 65GP High Density SRAM compiler families specifically optimized for MIPS32® processors, customers can speed development of complex SoCs targeted for Blu-ray DVD, HDTV, IPTV, set-top box and broadband customer premises equipment (CPE) devices.

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American Computer Aided Engineering Speeds Migration to Cadence Allegro

Posted by Ken Cheung in EDA Tools on Monday, March 29, 2010

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that it is teaming with American Computer Aided Engineering (AcAe), a dedicated CAD/CAE support services provider and design bureau, to assist customers transitioning from competing legacy CAD systems to Cadence® Allegro® PCB technologies and methodologies. With 24 years of experience in the electronic design automation industry, AcAe is helping Cadence PCB customers meet time-to-market commitments with design services and ease new product adoption as they migrate to and deploy Cadence Allegro technology.

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MoSys Acquires MagnaLynx for $5.0 Million

Posted by Ken Cheung in IP Cores on Friday, March 26, 2010

MoSys, Inc., (NASDAQ: MOSY), a leading provider of differentiated, high-density memory and high-speed interface (I/O) intellectual property (IP), announced that it has acquired MagnaLynx Inc. a developer of high-speed, low-power serial chip-to-chip communications technology. The total purchase price is expected to be approximately $5.0 million, including a milestone-based earn-out payment in 2011.

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Carbon Design Systems Unveils Databahn DDR SDRAM Controller IP Models

Posted by Ken Cheung in IP Cores,Models, Simulations on Friday, March 26, 2010

Denali Software, Inc., a leading provider of intellectual property (IP) and electronic design automation (EDA) software, and Carbon Design Systems announced a collaboration to provide designers with cycle-accurate models of Denali’s configurable Databahn[TM] DDR SDRAM controller IP for virtual platforms. Databahn IP models are available today for use with leading system simulation environments (including Carbon SoC Designer, CoWare Platform Architect, and OSCI SystemC) to perform architectural analysis, validate system performance, and perform hardware/software integration prior to silicon.

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Johns Hopkins University Tests LynxSecure for Real-Time Applications

Posted by Ken Cheung in RTOS on Friday, March 26, 2010

LynuxWorks[TM], Inc., a world leader in the embedded software market, announced that its LynxSecure separation kernel was independently tested with a series of performance tests at The Johns Hopkins University Applied Physics Laboratory (JHU/APL), to help assess the use of separation kernels for future real-time, mission-critical systems.

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