Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, announced the integration of the SpyGlass®-Constraints SDC equivalence verification capability into the production flow from the Semiconductor Technology Academic Research Center (STARC).
Atrenta’s SpyGlass-Constraints product offers a broad range of features to identify timing constraint issues in SoC designs. Capabilities range from constraint correctness and completeness checking through structural analysis and advanced formal techniques for the verification of timing exceptions.
The SpyGlass-Constraints SDC equivalence capability represents a significant enhancement to Atrenta’s existing timing constraint verification solution. By ensuring that timing constraints remain consistent with the design intent as the design undergoes transformations from RTL through final netlist, implementation iterations are reduced substantially.
SpyGlass-Constraints structural and formal verification capabilities are already incorporated into version 3.5 of the STARCAD-CEL reference flow. STARC engineers conducted an exhaustive evaluation of the new SDC equivalence checking capability on a broad range of test case designs, and were able to show that this technology added even further significant value.
“In our evaluations, we found that the SpyGlass-Constraints SDC equivalence capability allowed us to identify and fix a range of issues typically encountered when a design and its associated timing constraints are not maintained in a consistent manner,” said Nobuyuki Nishiguchi, vice president and general manager at STARC. “We view constraint verification as a continuous process – it is essential to be able to verify block level constraints in the context of a chip, and ensure that constraints remain applicable as the design undergoes transformations.”
“Atrenta is constantly enhancing its capabilities for Early Design Closure,” said Mike Gianfagna, vice president of marketing at Atrenta. “STARC’s rigorous qualification process for SpyGlass-Constraints has moved us a step closer to validating our value as a critical tool in chip design flows for accelerating timing closure.”
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure.