Cypress Semiconductor Corp. (NYSE:CY) announced its founder, president and CEO T.J. Rodgers will present the keynote address at the 2009 ARM® techcon3 in Santa Clara, California on Wednesday, October 21 at 12:00 p.m. at the Santa Clara Convention Center. The presentation, entitled “Not Your Father’s Embedded Design: How System-Level Programmability is Now Changing the Engineer’s World,” will examine how a new embedded design paradigm is enabling greater flexibility to address the rapidly changing market conditions and design demands facing engineers today.
Cypress will demonstrate its newly announced PSoC® 3 and PSoC 5 programmable system-on-chip architectures in booth 313 at the show from October 21-23. The new PSoC architectures dramatically increase performance and extend the world’s only programmable analog and digital embedded design platform, delivering unmatched time-to-market, integration, and flexibility across 8-, 16-, and 32-bit applications. This new embedded design platform is powered by the revolutionary PSoC Creator[tm] Integrated Development Environment, which introduces a unique schematic-based design methodology along with fully tested, pre-packaged analog and digital peripherals easily customizable through user-intuitive wizards and APIs to meet specific design requirements.
The live demonstrations show how the PSoC embedded design methodology helps engineers solve key challenges with precision analog, the PSoC Creator IDE and the PSoC ecosystem. For more information, visit www.cypress.com/go/pr/armtechcon3.
Additionally, two Cypress representatives will present three sessions during the conference:
“Reduce Power Consumption and Increase Processor Efficiency through Distributed Processing” – This presentation on Thursday, October 22 at 10:00 a.m. by Loren Hobbs, PSoC product marketing manager, discusses how an embedded system designer can reduce system power consumption and increase system efficiency and throughput through the use of distributed processing. By using the combination of a Direct Memory Access (DMA) engine and “mini-processors” to perform control algorithms, it is possible to create low power and highly efficient processing systems. By offloading the overhead of basic processing functions, the ARM processor is freed up to dedicate its instruction cycles to the more complex processing functions it is optimized for. This concept will be illustrated using examples of common functions in embedded systems, such as motor control.
“Low-power Programmable and Integrated Mixed-Signal Processing System Using an ARM Core” – This presentation on Friday, October 23 at 1:00 p.m. by Ata Khan, vice president of technical staff, shows how to build low-power programmable and integrated mixed-signal processing systems using an ARM Core. Applications such as sensors and control loops can require analog and digital signal conditioning and processing, and interaction with an embedded processor. Some representative applications, their requirements, and mapping to a proposed solution will be presented. Ideally, the elements required to build a low-power mixed-signal processing system should be integrated and interconnected allowing for the lowest power and best efficiency as well as an integrated development environment.
“A Painless Migration to 32-bit Designs” – This presentation on Wednesday, October 21 at 2:30 p.m. by Loren Hobbs will show how to evaluate the migration-readiness of a design and describe the latest techniques for ensuring a painless transition from 8-bits to 32-bits. Migrating from an 8-bit MCU to a 16-bit or 32-bit MCU poses significant challenges to embedded designers. Although 16- or 32-bit architectures can offer much greater flexibility with higher processing performance and data bandwidth, the required changes in board design and the need to learn new tools are often costly and time-consuming. Issues to be considered include whether the processor will be able to cope with an application’s unique demands, power consumption, pin compatibility, peripheral compatibility, tool migration, programming complexity, and availability of reference designs and code-ready development boards.
About PSoC 3 and PSoC 5
The new PSoC 3 and PSoC 5 architectures include high-precision programmable analog capability (up to 20-bit resolution for an Analog to Digital Converter) and expanded programmable digital resources integrated with powerful, industry-standard MCU cores and ample memory and communications peripherals. The PSoC 3 devices are based on a new, high-performance 8-bit 8051 processor, while the PSoC 5 devices include a powerful 32-bit ARM Cortex[tm]-M3 processor. The new products provide designers with a seamless, programmable design platform, enabling easy migration from 8 to 32 bits. The robust features of these new solutions dramatically expand the applications and markets that PSoC can address, including automotive, portable medical, industrial and many more. More information about PSoC products is available at www.cypress.com/psoc and free online training is at www.cypress.com/psoctraining.
Cypress delivers high-performance, mixed-signal, programmable solutions that provide customers with rapid time-to-market and exceptional system value. Cypress offerings include the PSoC® programmable system-on-chip, USB controllers, general-purpose programmable clocks and memories. Cypress also offers wired and wireless connectivity technologies ranging from its CyFi[tm] Low-Power RF solution, to West Bridge® and EZ-USB® FX2LP controllers that enhance connectivity and performance in multimedia handsets. Cypress serves numerous markets including consumer, computation, data communications, automotive, and industrial. Cypress trades on the NYSE under the ticker symbol CY.
Cypress, the Cypress logo, PSoC, CapSense, West Bridge and EZ-USB are registered trademarks and PSoC Creator and CyFi are trademarks of Cypress Semiconductor Corp.