NEC Electronics Corporation announced the successful development of a new architecture that can be used to provide both the miniaturization and the high accuracy to the analog circuits, including analog-to-digital (AD) and digital-to-analog (DA) converters. Advances in LSI miniaturization have brought about a system-on-chip (SoC), with a single SoC requiring a mixture of digital and analog circuits, increasing the numbers of embedded devices to shrink. As the SoCs scale down, overall power consumption decreases through lowered voltage and current, causing the poor matching characteristics between devices to increase relatively.
When digital signal is received, slight variations are ignored and the information is approximated to a certain precision, interpreted as discrete two digits, “0″ and “1″. Analog information, in contrast, is processed directly by analog components, so the system also receives the influence of noise and device mismatching that cause signal loss and distortion. Therefore, analog circuits cannot be expected to benefit from the CMOS miniaturization effect to the same extent as digital circuits.
To achieve miniaturization and high-accuracy in analog circuits, NEC Electronics developed a new architecture with folding technique and built-in self-calibrating feature that can realize a high-accuracy processing of the analog signals.
Applying the new architecture to analog-to-digital converters (ADCs), NEC Electronics successfully developed a 6-bit, 2.7 Giga samples per second (Gsps) ADC using the leading-edge 90 nm process, which is capable of high-speed processing with only half the power consumption previously only available with lower resolution ADCs.
As seen in TVs and mobile phones, digital technology has closely linked with our daily life. Yet, analog technology, such as processing of human interface components of displays and speakers, is still in heavy use all around us. High-speed and high-accuracy converter growth is also fueled by the spread of a high-speed broadband network, to securely track and hold the data within analog signal. At the same time, in response to the growing demand toward miniaturization and lower power consumption of portable devices, it has become essential to achieve miniaturization of analog circuits.
In order to resolve these issues, NEC Electronics developed a new technology, which is expected to be applied to such applications, and to support their realization.
The structural features of the newly developed ADC are as follows:
- Provides built-in parallel architecture of two channel folding ADCs to average and linearize the transfer characteristics
- Realizes digital error correction architecture through smooth digital transition of the two folding ADCs, ensuring high performance and low power consumption
In addition to these features, the newly developed ADC adopts a digital calibration algorithm that can correct the mismatches caused by the drift of environment and process variation, such as temperature changes. The new technology operates parallel with normal operation eliminating the need for additional calibration cycle.
NEC Electronics believes these new technologies will provide an architecture that is expected to result in further development of robust ADCs with lower power consumption. NEC Electrons will continue to advance its research and development activities in this area to put the developed technologies to practical use.
NEC Electronics will present the results of this research at the Symposium on VLSI Circuits, to be held at Kyoto, Japan from June 16 to June 18.
About NEC Electronics
NEC Electronics Corporation (TSE: 6723) specializes in semiconductor products encompassing advanced technology solutions for the high-end computing and broadband networking markets; system solutions for the mobile handset, PC peripheral, automotive and digital consumer markets; and multi-market solutions for a wide range of customer applications. NEC Electronics Corporation has subsidiaries worldwide including NEC Electronics America, Inc. and NEC Electronics (Europe) GmbH.