Mentor Graphics (Nasdaq: MENT) and Cadence Design Systems, Inc. (Nasdaq: CDNS) announced they have extended the Open Verification Methodology (OVM) to include the Unified Coverage Database (UCDB) application program interface (API) and an XML interchange format. The availability of the UCDB API and complementary XML interchange format documentation will allow verification teams to manage coverage metrics in a multi-tool, multi-vendor verification environment, and represents a step toward a standardized approach to managing coverage metrics.
Coverage metrics are used to quantify verification effectiveness and completeness, and to highlight areas of a design that require additional verification. Coverage metrics come from numerous sources, including simulation, static design checking, functional formal verification, sequential equivalence checking and emulation. Each verification tool creates coverage metrics that may be discrete, overlapping, or subsets of one another. With the UCDB API and the XML interchange format, verification teams are given the building blocks to manage the enormous amount of information generated during the verification process in a consistent manner with greater flexibility, and to tailor data transfer and analysis capabilities best suited to their tool and verification environment.
The Mentor/Cadence® extension to OVM matches their recent donations to the Accellera Unified Coverage Interoperability Standards (UCIS) technical subcommittee. Documentation for both the UCDB API and XML interchange format is available in the Community Contributions area of OVM World (www.ovmworld.org) under the Apache 2.0 license in keeping with OVM license terms. By using the Apache 2.0 license for this functionality, the specifications are available to everyone in the OVM ecosystem, and the Accellera UCIS technical subcommittee can easily access the specifications and any enhancements as it completes the standardization task.
About the Open Verification Methodology
The Open Verification Methodology, based on IEEE Std. 1800[tm] -2005 SystemVerilog standard, is the first open, language-interoperable, SystemVerilog verification methodology in the industry. It provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows. The OVM and OVM World began in August 2007 as a joint effort by Cadence Design Systems and Mentor Graphics.
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $850 million and employs approximately 4,450 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence is a registered trademark and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. Mentor Graphics is a registered trademark of Mentor Graphics Corporation.