Tensilica, Inc. will present a live webcast, “Everything You Wanted to Know About SOC Memory – But Forgot to Ask.” The webinar discusses the many alternatives for on-chip and off-chip memory usage that SOC designers must understand to develop successful multicore SOCs. The webinar will also highlight the essentials of SOC memory organizations for multicore designs, on-chip SRAM and DRAM, local memories and caches, on-chip non-volatile memories, and memory controllers for off-chip memory.
The presenter for the January 28th broadcast will be Steve Leibson, technology evangelist, Tensilica.
The live webcast will take place on Wednesday, January 28th at 11:00 a.m. PT / 2:00 p.m. ET. Afterwards, it will be available on demand from the EDN archives.
To attend the webcast, participants can register at www.tensilica.com/news_events/events.htm
Tensilica, Inc. is the recognized leader in customizable dataplane processors. Dataplane Processor Units (DPUs) consist of performance intensive DSP (audio, video, imaging, and baseband signal processing) and embedded RISC processing functions (security, networking, and deeply embedded control). The automated design tools behind all of Tensilica’s application specific processor cores enable rapid customization to meet specific dataplane performance targets. Tensilica’s DSPs and processors power top tier semiconductor companies, innovative start-ups, and system OEMs for high-volume products including mobile phones, consumer electronics devices (including portable media players, digital TV, and broadband set top boxes), computers, and storage, networking and communications equipment.