Atrenta Announces Design Closure Stimulus Package Seminars

Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, announced a worldwide Design Closure Stimulus Package seminar series. These seminars will assist chip companies to build better products, both faster and more economically, by detecting and mitigating design risks earlier in the design process than ever before.

Atrenta will visit major semiconductor hubs around the world to share the latest technologies and methodologies for Early Design Closure. The Design Closure Stimulus Package Seminar Series will extend through 2009 and 2010.

Presented by the company’s technology experts, these seminars will be aimed primarily at engineering managers, chip architects, RTL designers, design methodology engineers and IP design/verification engineers seeking to implement correct designs rapidly through the integrated use of a variety of design automation solutions. The free seminars, typically scheduled for 90 to 120 minutes during lunch, will cover a variety of topics, including clock domain crossing verification, design for test, constraints analysis, power management, modeling of physical effects at RTL and platform-based design techniques. Detailed case studies will demonstrate how to improve methodologies and achieve better Early Design Closure.

“We’re delighted to have the opportunity to share Atrenta’s expertise in Early Design Closure with a global audience,” said Mike Gianfagna, vice president of marketing at Atrenta. “These seminars are led by Atrenta’s internationally recognized experts and offer participants the latest information and tools to optimize leading edge chips before expensive and time-consuming detailed implementation.”

Pre-registration is required for these events. To find a listing of seminar dates and locations, and to register to attend one of these no-cost sessions, please go to www.atrenta.com/stimulus_package

Seminar Schedule
Following is the list of currently scheduled seminars:

  • Catching CDC & DFT Bugs, Thurs, Jan 29, 2009 in Noida, India, and Mon, Feb 2, 2009 in Bangalore, India
  • Eliminate Power Bugs & Hogs, Thurs, Feb 5, 2009 in Santa Clara, India

About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure.

Atrenta, the Atrenta logo, SpyGlass, 1Team, and Early Design Closure are registered trademarks of Atrenta Inc.