DesignCon Features Si2 Low Power Coalition Tutorial

The Silicon Integration Initiative (Si2) announced a Low Power Coalition Tutorial being hosted at the DesignCon Conference to be held at the Santa Clara Convention Center in Santa Clara, CA. The “Low Power Flows and Formats, From ESL to Implementation” Tutorial will be held on Monday, February 2, 1:30 pm – 4:30 pm in Room 203 in the Santa Clara Convention Center.

Green technologies, including low power design, have been identified as critical areas for design flow improvement in IC and system design. This three hour tutorial is intended to review the progress made to date in the areas of low power design formats and to expose and acknowledge the challenges remaining for full interoperability between those formats. Detailed presentations on advances in low power design understanding will be made at the workshop and specific areas of interoperability that remain will be addressed. Advances in Power Aware design flows and Low power design techniques will be presented and supporting documents and technologies will be made available. The tutorial will conclude with a panel discussion on “What does interoperability mean?” The goal of the tutorial is to enhance industry understanding of the state of low power design capabilities today and the remaining challenges to full interoperability of low power design flows that will need to be addressed.

Agenda:
Introduction, Resources, Agenda: Nick English, Si2
CPF 1.1 Summary and CPF 1.2 Roadmap, Qi Wang, Cadence
Power Aware Flows and Design Techniques, Nagu Dhanwada, IBM
P1801 Update, Gary Delp, LSI
Atrenta’s Experience with multiple Formats: Dave Allen, Atrenta
Panel: What does interoperability mean to you? (Above speakers, as well as Dale Pollek, Atrenta)

To register for DesignCon Conference Events, go to this link: www.designcon.com/2009/register/.

Another Si2-sponsored event at DesignCon is the Si2 Member/Guest Meeting immediately following the tutorial in the same room. This meeting is open to all. For more information: www.si2.org/?page=11.

About the Low Power Coalition (LPC)
The Low-Power Coalition (LPC) is delivering enhanced capabilities in low-power Integrated Circuit (IC) design flows in particular relating to specifications of low-power design intent, architectural tradeoffs, logical/physical implementation, design verification and testability. Member companies are: Advanced Micro Devices (NYSE: AMD), ARM (Nasdaq: ARMHY), Atrenta, Azuro, Cadence Design Systems (Nasdaq: CDNS), Calypto Design Systems, Entasys, Envis, IBM (NYSE: IBM), Global UniChip Corporation, LSI (NYSE: LSI), NXP Semiconductors, Sequence Design, and Virage Logic (Nasdaq: VIRL).

About Si2
Si2 is an organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time-to market, reduce costs, and meet the challenges of sub-micron design. Si2 is uniquely positioned to enable collaboration through a strong implementation focus driven by its member companies. Si2 focuses on developing practical technology solutions to industry challenges. Si2 represents companies involved in all parts of the silicon supply chain throughout the world.