Atrenta CEO to Tame SoC Design Through Abstraction at VLSI Conference

Ajoy Bose, chairman, president and CEO of Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, will deliver a keynote address here at the VLSI conference on January 7, 2009. The VLSI conference is a forum for researchers and designers to present and discuss various aspects of VLSI design, electronic design automation, enabling technologies, and embedded systems.

In his presentation titled “Taming SoC design through abstraction: What the past has taught us about the future” Dr. Bose will discuss the trends of moving design abstraction to the next higher level, and assess what these trends mean in the context of the current challenges before us.

“Today, we are at a crossroads in the evolution of design. We need a well-defined strategy to address design complexity challenges,” said Ajoy Bose. “While optimizing transistor geometries, “variability aware” physical implementation tools and design reuse strategies contribute to the solution, they all miss the primary force of design evolution. Over the past 30 years or so, it has been proven time and again that moving design abstraction to the next higher level is required if technology is to advance. In my keynote, I will be discussing several important trends that offer the potential to put the customer back in charge of their design.”

Atrenta will also be on the show floor at booth # 1 at the VLSI conference. Through presentations, attendees will learn about Atrenta’s Early Design Closure solutions that allow design capture, verification, optimization and exploration early in the design flow at the register transfer language (RTL) stage, when it’s faster and easier to correct problems and explore alternatives. This approach facilitates propagation of design efficiencies to detailed, back-end implementation, with minimized schedule risk.

About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. For more information, visit www.atrenta.com

Atrenta, the Atrenta logo, SpyGlass, 1Team, and Early Design Closure are registered trademarks of Atrenta Inc.