Aldec, Inc., a 24-year-old EDA company, announced the release of ALINT 2008.10, a VHDL and Verilog Design Rule Checking Tool used to analyze HDL source code against a comprehensive set of ASIC design guidelines for early bug detection. ALINT reduces risk when developing complex multi-million gate ASICs by resolving structural, coding and consistency problems early in the design cycle. ALINT 2008.10 delivers support for VHDL, Verilog and Mixed-Language designs, cross-probing between the source code and error messages, advanced rule configuration and result analysis.
Design Rule Support
ALINT 2008.10 complies with STARC® RTL Design Style Guide for both VHDL and Verilog. STARC is a consortium of 11 Japanese ASIC foundries that has established a set of design guidelines for corporations to follow based on a set of best-design practices. When both VHDL and Verilog Rule Libraries are combined, ALINT 2008.10 can run Mixed-Language Design Rule Checking.
Advanced Rule Configuration
ALINT 2008.10 enables total visibility and configuration of design rules through its unique Ruleset/Policy Editors and Rule Parameters/Descriptions Viewers. Engineers can customize the properties of rules and have visibility into each rule including rule number, rule level, rule title and a short rule description. Rule parameter values can be changed by double-clicking on the rule parameter. Rules may be combined together in different ways to form rule sets and policies that are treated by ALINT as a single object. Rules may be easily dragged and dropped to form rulesets or policies.
For violation analysis, the Violation Viewer, in ALINT 2008.10, enables engineers to view all violations that occur in source code. Double-clicking on any violation reported in the Violation Viewer cross-probes directly to the line of HDL source code that caused the violation. A summary of all violations can be viewed within the Violation Viewer at all times. Violation reports are printable and exportable to TXT, HTML or CSV file types.
ALINT 2008.10 is available today and is sold directly from Aldec and its authorized worldwide distributors. To obtain the latest VHDL and Verilog Rule Libraries supported it is recommended to Download a FREE evaluation copy of ALINT 2008.10. A complete list of all rules and their descriptions are available.
Aldec Corporation is an industry leader in electronic design verification and offers a patented technology suite including: design entry, HDL simulators, hardware-assisted verification, design rule checking, co-simulation, co-verification, IP Cores, DO-254 compliance tool sets and engineering specialty solutions.
ALINT and Aldec are trademarks of Aldec, Inc.