Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced the release of an open-source SystemVerilog solution to help users include Synopsys’ Verification Methodology Manual verification IP (VMM VIP) as they adopt the advanced environments supported by the Open Verification Methodology (OVM). This solution leverages investment in existing verification components in order to take advantage of the industry-leading features of the OVM and its vibrant ecosystem. These features include verification language interoperability, scaling from block to system, inter-component communication using transaction-level modeling, and advanced object-oriented capabilities for reuse and customization of these components.
“The verification ecosystem has enthusiastically recognized the superior features of the OVM,” said Michal Siwinski, Verification Solution and Product Marketing group director at Cadence. “We are seeing a growing demand for assistance in adopting the OVM, especially given the tremendous breadth of Cadence’s line of verification IP. This new solution arises directly from our experiences helping customers move from VMM VIP testbenches to the OVM with minimal recoding. We are making it available as open source as a way to invite more VMM VIP users to share in the benefits of the OVM.”
The Cadence solution, built on top of the OVM 2.0 release, lets users run both OVM and VMM VIP within a single OVM environment. The OVM environment configures the VMM VIP, which communicates using both OVM sequences and virtual sequences, and uses the OVM message utility.
“We have a lot of experience in both methodologies and find clear advantages in the OVM,” said Adrian Coman, CEO of TrustIC. “Increasingly, our customers use our services to move to the OVM, and that places us in a unique position. We have evaluated the Cadence solution and find it to be excellent for enabling OVM productivity.”
As an active member of the Accellera VIP Technical Subcommittee (TSC), Cadence has worked with other committee members to define the requirements for interoperability among different verification methodologies. The Cadence solution is freely available to all Accellera VIP TSC members as a proof-of-concept implementation meeting their requirements.
The SystemVerilog source code and documentation are available immediately in the “Community Contributions” area of the OVM World site at www.ovmworld.org.
About the Open Verification Methodology
The Open Verification Methodology is the first open, language-interoperable verification methodology in the industry. It provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows. The OVM is supported by more than 50 companies offering training, services, and products.
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence is a registered trademark and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries.