At the first annual FPGA Summit coming to San Jose next week, GateRocket executives Dave Orecchio, CEO; and Chris Schalick, CTO will participate in tutorial and technical sessions on the thorny issue of FPGA verification and debug. Orecchio is hosting tutorial session T3B at 2:40 PM on Wednesday afternoon with experts from Mentor Graphics, GateRocket, Altera, Agilent Technologies and Xilinx. The FPGA Summit runs Dec. 9-11 in San Jose, Calif.
“FPGA verification and debug is the number-one issue that affects time-to-market of FPGA based products,” Orecchio said. “I’m pleased to have this opportunity to share some of the new techniques and products to speed verification and debug now available from GateRocket,” he added.
“I am grateful to the organizers of this new and exciting conference for giving us the chance to discuss how designers can quickly eliminate the verification bottleneck and significantly reduce in-system debug time,” said Schalick.
The FPGA Summit will focus on the latest hardware and design news in the FPGA world and includes three days of technical sessions and impressive keynote speakers. GateRocket’s Orecchio will participate in Wednesday’s (Dec. 10) Verification Tutorial and hold court as the Summit’s designated “Verification Expert” during Wednesday night’s reception. CTO Schalick will speak on the topic of Hardware Assisted Verification Wednesday afternoon. For more information on the FPGA Summit and a detailed conference program: www.fpgasummit.com.
GateRocket, Inc., located in Bedford, Mass., offers electronic engineers the first Device Native verification and debug solution for advanced FPGA semiconductor devices. The company’s RocketDrive enables users to verify and debug advanced FPGA designs faster and with higher quality for greatly improved time to market, and more reliable results.