Si2 Unveils Power-Aware Design Flow, Low Power Design Documents

Silicon Integration Initiative (Si2) has released two documents on Power Aware Design Flows and Low Power Design Techniques developed by its Low Power Coalition (LPC). Both documents are available to the industry on the Si2 web site links as noted below. The first document, “Si2 Power Aware Design Flows,” outlines a best practices approach adopted by much of the industry regarding Power Aware Design Flows and the points in the flow for power closure decisions. This information provides a description of the current state of the art in ESL algorithms and system models, RTL design and IP integration, as well as physical implementation and synthesis in regards to power-aware design flows.

The second document, “Si2 Power Reduction Stimulus and Low Power Design Techniques,” identifies and lists all known low power techniques used in minimizing power consumption in silicon and systems. The document is intended to drive the flow and format requirements and reach convergence in the areas of Pre and Post Silicon Design. All low power techniques are classified in five categories. Clock techniques are related to optimal usage of clocks. Activity control related techniques are different hooks to monitor and control activities. Voltage Techniques are related to control of operating voltage and power gating in the silicon and systems. Circuits and process are related to manufacturing processes and special circuit usage in silicon. Firmware techniques are related to software and hardware integrations in system design.

“These important documents highlight the valuable work the LPC is doing beyond the maintenance and expansion of the Common Power Format Si2 standard,” said Steve Schulz, president and CEO, Si2. “The commitment and support of the LPC working groups in producing these documents gives evidence to the relevance of the LPC and its critical mission.”

Following are links to each document:
Si2 Power Aware Design Flows:
Si2 Power Reduction Stimulus and Low Power Design Techniques:

The Low Power Coalition is an open industry group operating under the auspices of Si2. All interested parties are invited to join existing LPC members and participate.

About the Low Power Coalition (LPC)
The Low-Power Coalition (LPC) is delivering enhanced capabilities in low-power Integrated Circuit (IC) design flows in particular relating to specifications of low-power design intent, architectural tradeoffs, logical/physical implementation, design verification and testability. Member companies are: Advanced Micro Devices (NYSE: AMD), ARM (Nasdaq: ARMHY), Atrenta, Azuro, Cadence Design Systems (Nasdaq: CDNS), Calypto Design Systems, ChipVision Design Systems, Entasys, Envis, Freescale Semiconductor, Global Unichip, IBM (NYSE: IBM), Intel (Nasdaq: INTC), LSI Corporation (NYSE: LSI), NXP Semiconductors, Sequence Design, and Virage Logic (Nasdaq: VIRL). The Low Power Coalition is an open industry group operating under the auspices of Si2. All interested parties are invited to join existing LPC members and participate.

About Si2
Si2 is an organization of industry-leading semiconductor, systems, EDA, and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time to market, reduce costs, and meet the challenges of sub-micron design. Si2 is uniquely positioned to enable collaboration through a strong implementation focus driven by its member companies. Si2 focuses on developing practical technology solutions to industry challenges. Si2 represents nearly 100 companies involved in all parts of the silicon supply chain throughout the world.