Aldec, Inc., a leader in mixed-language HDL simulation for ASIC and FPGA devices, is pleased to announce that it is now an official partner on OVM World, the community site for the Open Verification Methodology (OVM). This partnership will enable Aldec to offer support for OVM 2.0, the first open, language-interoperable verification methodology, co-developed by Cadence Design Systems, Inc. (NASDAQ: CDNS). This OVM-based release of the Aldec mixed-language HDL simulator will provide the OVM community additional choices and further reinforce the value of a widely supported open-source methodology. Aldec plans to integrate OVM 2.0 into its common-kernel, mixed-language, HDL simulator on the Windows® and Linux® 32/64 platforms.
“Aldec is pleased to announce our integration of the OVM 2.0 into our flagship mixed-language HDL simulation product line. Aldec will bring OVM 2.0 to the mass market with its products that continue to grow within the high-density FPGA design community. Our customers will greatly benefit, applying the most-advanced open verification methodology in the world to their designs,” said Lori Nguyen, Director of Marketing of Aldec, Inc.
“Cadence is extremely pleased to see Aldec fully support the OVM, enabling their customers to build scaleable advanced verification environments,” said Michal Siwinski, Group Marketing Director for advanced verification at Cadence. “This move by Aldec is showing the OVM ecosystem that convergence to a common, open methodology is not only possible, it’s here now. Users can focus on the task at hand – functional verification – and not worry about which approach is the right one.”
Aldec OVM 2.0 Support
SystemVerilog users of Aldec tools will benefit from the OVM’s multi-language support of Transaction-Level Modeling (TLM), previously available only for SystemC. All foundation-level utilities, standard TLM interfaces and built-in debug support for TLM connections will enable Aldec users to build advanced object-oriented, coverage-driven verification environments in SystemVerilog. The Aldec simulation suite will support both the OVM 2.0 class library and methodology, helping engineers develop reusable, interoperable verification IP and create hierarchical environments that facilitate “plug-and-play” reusable verification.
A preliminary release of the Aldec HDL Simulator Riviera-PRO[tm], supporting OVM 2.0, is scheduled for delivery in Q1 2009.
About the Open Verification Methodology (OVM)
The Open Verification Methodology is the first open, language-interoperable verification methodology in the industry. It provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows.
Aldec Corporation is an industry leader in electronic design and offers a patented technology suite including: design entry, HDL simulators, hardware-assisted verification, design rule checking, co-simulation, co-verification, IP Cores, DO-254 compliance tool sets and engineering specialty solutions. Aldec is “The Best Value in EDA” providing 24 years of proven, cost-effective verification. Aldec is a privately held company with continuous revenue growth and employs approximately 200 people worldwide.
Riviera-PRO and Aldec are trademarks of Aldec, Inc.