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Archive for October 2008

Microchip Launches MPLAB ICD 3 High-Speed In-Circuit Debugger

Posted by Ken Cheung in Test Solution on Wednesday, October 29, 2008

Microchip Technology Inc., a leading provider of microcontroller and analog semiconductors, announced from the Embedded Systems Conference in Boston the MPLAB® ICD 3 — a cost-effective, high-speed development tool that supports in-circuit programming and debugging of Microchip’s Flash-based 8-bit PIC® microcontrollers (MCUs), and its entire line of 16- and 32-bit MCUs and 16-bit dsPIC® Digital Signal Controllers (DSCs). With robust system capabilities and high-speed circuitry, the MPLAB ICD 3 offers full compatibility with the MPLAB Integrated Development Environment (IDE), exceptional programming speed and reliability.

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Axell, Beceem, EDA Express, Magillem, MtekVision, Verilab Join OCP-IP

Posted by Ken Cheung in IP Cores on Wednesday, October 29, 2008

Open Core Protocol International Partnership (OCP-IP) announced that Axell Corporation, Beceem, EDA Express, Magillem Design Services, MtekVision, and Verilab have joined the organization. The six new members illustrate the strong support and industry-wide adoption of the OCP standard.

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Timesys Offers LinuxLink Support for Freescale i.MX31 PDK

Posted by Ken Cheung in RTOS on Wednesday, October 29, 2008

Timesys Corporation, a premier provider of embedded Linux software solutions, announced LinuxLink support for the Freescale i.MX31 PDK. Based on Freescale’s i.MX family of multimedia processors, LinuxLink for the i.MX31 PDK leverages the system’s powerful suite of high-performance multimedia features, including audio, video and image processing.

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Hitachi Lowers Manufacturing Cost with Cadence Encounter Test

Posted by Ken Cheung in Test Solution on Wednesday, October 29, 2008

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that its unique test technologies have enabled Hitachi Ltd., in the hardware domain of Information & Telecommunication Systems, to cost-effectively produce high-performance large scale integrated circuit (LSI) devices in volume with the lowest number of test escapes or defects achieved by Hitachi to date. By combining Cadence® Encounter® Test pattern-fault modeling with the state-of-the-art test pattern generation, compression technology and diagnostics, Cadence helps Hitachi ensure that these complex, high-performance LSI devices work as designed.

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Moai Electronics Deploys Cadence Encounter RTL Compiler, Encounter Test

Posted by Ken Cheung in EDA Tools on Wednesday, October 29, 2008

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced Moai Electronics Co., a leading IC design company in Taiwan, has deployed Cadence® Encounter® RTL Compiler and Encounter Test to successfully tape out a flash memory controller with dramatically faster time to market, lower test costs, and higher quality.

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Evatronix Announces USBHS-HUB Hi-Speed USB Embedded Hub Controller

Posted by Ken Cheung in IP Cores on Wednesday, October 29, 2008

The Silicon Intellectual Property (IP) provider, Evatronix SA, announced the USBHS-HUB – a Hi-Speed USB Embedded Hub Controller to support the full range of USB host applications. Thanks to a variety of functional features that have been implemented in the IP core, the controller increases the number of USB Hi-Speed host ports that can be used to connect any USB device.

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SEMATECH Receives Telius SP UD System from Tokyo Electron Limited

Posted by Ken Cheung in Research on Wednesday, October 29, 2008

SEMATECH, in partnership with the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, is pleased to announce that it has received a 300 mm Telius[tm] SP UD system from Tokyo Electron Limited (TEL). The Telius SP UD system is the latest generation through-silicon-via (TSV) etch tool that has the versatility to investigate various chemistries to etch vias ranging from sub 1 micron to tens of microns wide. The TSV RIE tool, which is a critical component of all 3D TSV integration schemes, will be used in SEMATECH’s 3D R&D Center at CNSE’s Albany NanoTech Complex in Albany, NY.

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PrismTech Rolls Out Spectra 2.1 for Software Defined Radio

Posted by Ken Cheung in EDA Tools on Wednesday, October 29, 2008

PrismTech[tm] announced the release of Spectra[tm] 2.1, the next version of its market-leading Spectra product suite for Software Defined Radio (SDR) developers. PrismTech’s products power netcentricity by optimizing resource management and providing superior communications and data management. Spectra 2.1 delivers new and unrivalled levels of Software Communications Architecture (SCA) developer productivity, SCA compliance validation and SCA operating environment (OE) performance. It is simply the most productive, standards-compliant and optimized SCA developer and OE product suite available.

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Xilinx Unveils Virtex-5 FXT FPGA ML510 Embedded Development Platform

Posted by Ken Cheung in FPGAs on Wednesday, October 29, 2008

Xilinx, Inc. (Nasdaq: XLNX) announced its Virtex-5 FXT FPGA ML510 Embedded Development Platform for developing high-performance embedded systems driven by dual processors. Built around the Virtex-5 FXT FPGA platform with its two integrated Power PC(R) 440 processors and supported by Linux and VxWorks operating systems, the new development platform provides software and hardware design teams with unprecedented levels of flexibility and computational capacity.

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Accverinos Accelerates ASIC Prototypes with Altera Stratix III FPGAs

Posted by Ken Cheung in FPGAs on Wednesday, October 29, 2008

Altera Corporation (NASDAQ:ALTR) announced Accverinos Co., Ltd. is using Stratix® III FPGAs in its latest family of ASIC prototyping boards. The All-in-One Baseboard B-11, Stratix III edition, which features an Altera® EP3SL340 FPGA, offers design engineers a verification platform rich with logic, memory and digital signal processing (DSP). Designers developing high-performance video and imaging, communications and industrial applications can use Stratix III devices as ASIC prototypes that run at or near system speeds.

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