Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that its unique test technologies have enabled Hitachi Ltd., in the hardware domain of Information & Telecommunication Systems, to cost-effectively produce high-performance large scale integrated circuit (LSI) devices in volume with the lowest number of test escapes or defects achieved by Hitachi to date. By combining Cadence® Encounter® Test pattern-fault modeling with the state-of-the-art test pattern generation, compression technology and diagnostics, Cadence helps Hitachi ensure that these complex, high-performance LSI devices work as designed.
Working together, Cadence and Hitachi have significantly advanced LSI device quality through innovative test methodologies. By combining Cadence’s unique pattern fault modeling technology, SDF-based dynamic test generation, and OPMISR+ compression with Hitachi’s test methodology, the two companies produced test vector compression results exceeding 300X. This matches industry compression requirements set for 2011, according to an ITRS industry survey published in 2007. In addition, the test coverage results for single-stuck-at-fault, delay-based and bridge fault exceeded Hitachi’s requirements.
Combined with the industry-leading Cadence diagnostic solution, the fault modeling and compression technologies result in faster yield ramps and more accurate and efficient vector sets than previous solutions. The increased accuracy leads to fewer test escapes, eliminating the need for time-consuming iterative debug and refinement loops to achieve high-quality test patterns.
“Through the Cadence Encounter Test pattern fault model and advanced test compression technology, we were able to achieve better test quality and meet our test cost requirements,” said Toru Hiyama, general manager, Hardware MONOZUKURI Division at Hitachi, Ltd. “Our requirements were extremely aggressive, with challenges requiring advanced knowledge and leading technology capabilities, so we were really happy when the Encounter Test team was able to come through.”
“Cadence Encounter Test solutions are production-proven for advanced semiconductor designs,” said Sanjiv Taneja, vice president, Encounter Test at Cadence. “Our strategy is to drive physical and process awareness into front-end design not only for physical implementation but for test pattern generation as well. Each path requires advanced modeling for quality, accuracy, and improved run times to provide high-quality, cost-effective solutions that result in greater profitability for our customers. This is a key combination in this era of nanometer design.”
Cadence will demonstrate both Encounter True-Time Test ATPG and Encounter Test compression technology in Booth #221 at the International Test Conference (ITC) 2008, being held at the Santa Clara Convention Center, Oct. 28-30.
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence and Encounter are registered trademarks, and the Cadence logo is a trademark, of Cadence in the United States and other countries.