SEMATECH Reveals Speakers for 3D IC Design and Test Workshop

IC manufacturers, electronic design automation (EDA) professionals and product and test engineers will gather at an upcoming SEMATECH-sponsored workshop to hear industry leaders address the most pressing design and test issues in 3D and TSV integration. The SEMATECH workshop, “Design and Test Challenges for 3D ICs,” will be held in conjunction with the IEEE/ACM 2008 International Conference on Computer-Aided Design on November 13 in San Jose, California. The event is co-sponsored by the ACM/SIGDA Physical Design Technical Committee.

The line-up of experts from a cross-section of the 3D design and test community, and the critical issues they will explore, include:

  • 3D Market Overview, Jan Vardaman, TechSearch
  • The Challenges of Design and Test of the 80 Core Chip, Tanay Karnik, Intel
  • 3D Integration – Opportunities and Challenges, Koushik Das, IBM Research
  • Reliable Power Delivery for 3D Integrated Circuits, Sachin S. Sapatnekar, University of Minnesota
  • Thermal Challenges and Solutions for 3D ICs, Edmund Cheng, Gradient
  • Cost Analysis and Design Exploration for 3D ICs, Yuan Xie, Penn State University
  • Memory Rich Application Exploration for 3D Integration, Paul Franzon, North Carolina State University
  • 3D-DRAM Circuit Design, Modeling and Exploration for Computer Memory Hierarchy, Tong Zhang, RPI
  • Test and Design for Test of 3D ICs, Prasad Mantri, SUN
  • Testing Options for 3D devices that use Through Silicon Stacking, Michael Laisne, Qualcomm

“The objectives of this workshop are to clarify the nature of the design and test challenges for 3D ICs, both near- and long-term, and to assess the state of the industry to support 3D IC design and test,” said Larry Smith, workshop chairman and SEMATECH’s 3D reliability and product interlock expert. “This support will be critical to achieving the full potential and the widespread adoption of this technology.”

The day-long workshop will conclude with a panel discussion on how the EDA industry is responding to TSVs, which will feature experts from leading commercial semiconductor and EDA companies. The panel will explore whether the design needs for stacked die systems represent an evolution or a discontinuity for the EDA industry, and will examine these alternatives by looking at EDA vendor strategies and the needs of design teams involved in TSV-based systems.

“The readiness of 3D EDA design software tools is one of several barriers to entry for full-scale 3D IC integration,” said David Kung, senior manager, Design Automation at IBM. “SEMATECH’s forum provides the insight we need to evaluate current developments in the industry to support 3D IC design and test.”

“The need for the appropriate electronic design automation tools and design methodologies is moving to the forefront as one of the key technological challenges for 3D and TSV integration,” said Riko Radojcic, leader of DFx projects at Qualcomm. “We need to continue examining the 3D design methodologies and flows, and their technical challenges, the need for specific design tools and how to collaborate with EDA vendors to enable a suitable revision of existing design flows. The 3D Design and Test Workshop is one of the very good platforms for industry leaders to continue building consensus and action plans related to these issues.”

SEMATECH hosts a variety of forums to accelerate the adoption of these technologies and to drive industry consensus on the different 3D options. The Design and Test Challenges workshop completes a successful series of three SEMATECH-sponsored 3D workshops in 2008, including Equipment Challenges for 3D Interconnect and Manufacturing and Reliability Challenges for 3D ICs using TSVs.

SEMATECH’s 3D program encompasses equipment evaluations, unit processes, integration and metrology. To learn more about the Design and Test Challenges for 3D ICs workshop, including registration and program information, please visit

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