Lattice Semiconductor Debuts LatticeECP2M PCI Express Development Kit

Lattice Semiconductor (NASDAQ: LSCC) announced the availability of a new low cost PCI Express development kit for its LatticeECP2M[tm] family of low cost 90nm FPGAs. Based on a new PCI Express x1/x4 evaluation board, the kit accelerates development of PCI Express designs using the LatticeECP2M family. The kit has been developed from the ground up to accelerate the evaluation of Lattice PCI Express technology, demonstrate a range of solutions matching typical application requirements and speed users to design exploration.

The new kit includes four key capabilities for quick evaluation and rapid, low cost PCI Express system design. First, the kit enables users to bring up running PCI Express hardware in thirty minutes or less. Second, various demo executables address control plane through data plane performance requirements. Third, source files for the demos are available that enable rebuilding designs up to a known good starting point. Finally, the kit enables a rapid transition to design exploration through the included software tools, IP enabled evaluation process and project source directories.

“The new LatticeECP2M PCI Express development kit is a prime example of how Lattice delivers a targeted solution to FPGA designers,” said Sean Riley, Lattice Corporate Vice President and General Manager of High Density Solutions. “The LatticeECP2M family provides a cost-effective alternative to the high-end SERDES-based FPGAs and ASSPs that traditionally have been used for PCI Express applications. With this new development kit, designers can rapidly evaluate, develop and prototype their PCI Express applications using LatticeECP2M devices.”

Pricing and Availability
The development kit is available now, with a list price of $895.00. The kit can be ordered through Lattice sales or through the Lattice on-line store at

About the LatticeECP2M PCI Express Development Kit
The new LatticeECP2M PCI Express development kit is the first in a series of development kits that will support Lattice devices and enable users to obtain working hardware in thirty minutes and then a known good starting point for a design in under two hours. There are several demos available, including a control plane application, a throughput demo for high-bandwidth applications, and two demos supporting scatter-gather DMA capabilities: a color bar demo and an image transfer demo (which also makes use of the Lattice Scatter-Gather DMA IP core).

All of the demos use the just released LatticeECP2M PCI Express x1/x4 Endpoint ispLeverCORE[tm] IP, version 3.3. The included low cost LatticeECP2M PCI Express x1/x4 evaluation board has been optimized with several features designed to make the evaluation process more productive, including support of both x1 and x4 link edge card fingers and LEDs for each link that are visible from outside the PC chassis to indicate whether the link is active. Also included are a 60-day evaluation license for Lattice’s ispLEVER® software design tools (for new users), the ability to evaluate the new LatticeECP2M PCI Express ispLeverCORE IP and project source directories, all of which can be used to create a template for design exploration.

About LatticeECP2M FPGAs
LatticeECP2M FPGAs are an innovative response to the broad range of customers who have been clamoring for low cost SERDES capability for chip-to-chip and small form-factor backplane applications. The LatticeECP2M family maintains all of the compelling features of the 90nm LatticeECP2[tm] family that are required for high-volume, cost-sensitive applications, while dramatically increasing memory capacity (ranging from 1.2 Mbits to 5.3 Mbits) and DSP resources (ranging from 24 to 168 multipliers).

The SERDES integrated into the LatticeECP2M devices has been engineered as a quad-based architecture with 1 to 4 quads, depending on the size of the device. Each quad features four SERDES channels (four complete TX and RX channels), with each channel featuring power consumption as low as 100mW and supporting data rates from 270 Mbps to 3.125 Gbps. A flexible PCS layer that includes 8b/10b encoding, an Ethernet link state machine and rate matching circuitry also are built onto the chip. The SERDES/PCS combination is designed to support today’s most common packet-based protocols, including PCI Express, Gigabit Ethernet, Serial RapidIO and wireless interface standards (OBSAI and CPRI).

Lattice Semiconductor’s innovative programmable logic solutions include FPGAs, CPLDs and Mixed Signal devices.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeECP2, LatticECP2M, ispLEVER, ispLeverCORE and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.