Virage Logic, TSMC Expand Process Optimized IP Agreement

Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry’s trusted IP partner, and TSMC, the world’s largest dedicated semiconductor foundry, have extended their agreement to provide end-market process optimized intellectual property (IP) for System-on-Chip (SoC) designs for both mainstream and advanced process technologies. Under the expanded agreement, Virage Logic will develop physical IP, such as embedded memories and logic libraries, for both new and optimized processes ranging from 180-nanometer (nm) to 40nm. The collaboration enables Virage Logic and TSMC to more quickly meet their customers’ shifting and stringent application-specific requirements.

“We value Virage Logic’s extensive expertise and ability to work with our mutual customers to create specialized IP that meets their aggressive design requirements and narrow market windows,” said ST Juang, senior director, Design Infrastructure Marketing, TSMC. “Together we will be able to offer differentiated IP.”

“TSMC and Virage Logic are responding to the global semiconductor industry’s need to have optimized IP available concurrently with optimized process availability,” said Brani Buric, executive vice president of marketing, Virage Logic. “This latest expansion of our long-standing relationship is yet another example of how we are collaborating to provide our mutual customers with a competitive advantage.”

Today’s announcement showcases the depth of the companies’ relationship and follows several recent noteworthy announcements the companies have made.

Virage Logic is a leading provider of semiconductor intellectual property (IP) for the design of complex integrated circuits. The company’s highly differentiated product portfolio includes embedded SRAMs, embedded NVMs, embedded test and repair, logic libraries, memory development software, and DDR memory controller subsystems. As the industry’s trusted semiconductor IP partner, foundries, IDMs and fabless customers rely on Virage Logic to achieve higher performance, lower power, higher density and optimal yield, as well as shorten time-to-market and time-to-volume.