Tensilica, Cadence Team on CPF-Enabled Flow for Multimedia Subsystems

Tensilica,® Inc. announced that they have collaborated with Cadence (NASDAQ: CDNS) to create a Common Power Format (CPF)-enabled low-power reference design for a multimedia subsystem based upon its popular 330HiFi Audio Processor and 388VDO Video Engine. Cadence and Tensilica engineers worked together to develop an implementation of the Tensilica multiprocessor audio-video platform using the complete Cadence Low-Power Solution including Encounter® RTL Compiler global synthesis, Encounter Conformal Low Power and the SoC Encounter® RTL-to-GDSII system.

The 388VDO Video Engine is a fully programmable codec processor that supports multi-standard, multi-resolution video. Both are targeted at mobile handsets and personal media players (PMPs). Now, SoC designers can now build upon the Tensilica reference design by employing the Cadence Low-Power Solution to deliver the lowest-power implementation for power-sensitive mobile applications.

“The combination of Tensilica IP with the Cadence Low-Power Solution equips customers with all the tools and technology they need to create power-efficient, portable multimedia chips,” stated Chris Jones, Tensilica’s director of strategic alliances. “By using this reference flow based on the widely deployed Common Power Format, our customers will be able to save precious design time while employing the most advanced techniques for low-power design.”

“Tensilica has been an active participant in the Power Forward Initiative which has the goal of enabling the design and production of more power-efficient electronic devices,” said Pankaj Mayor, group director of Business Enablement at Cadence Design Systems, Inc. “This proof point project demonstrates that by using CPF with the Tensilica processor and the Cadence Low-Power Solution, multimedia chip designers can accelerate delivery of ultra-low-power products to their markets.”

For 330HiFi and 388VDO users, Tensilica will deliver example reference scripts for Encounter RTL Compiler global synthesis, Encounter Conformal Low Power and the SoC Encounter RTL-to-GDSII system, along with example CPF files describing power intent for the 388VDO processor. The CPF package will be available in the fourth quarter of 2008.

About Tensilica
Tensilica, Inc., is the recognized leader in customizable applications processors, DSPs and standard IP cores for audio, video, imaging, security, networking, and baseband signal processing. The automated design tools behind all of Tensilica’s customizable applications processor cores powers top tier semiconductor companies, innovative start-ups, and system OEMs for high-volume products including mobile phones, consumer electronics devices (including portable media players, digital TV, and broadband set top boxes), computers, and storage, networking and communications equipment.

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