Design and Verification Conference Issues Call for Papers

Posted by EDA Geek News Staff in Events, Training on Wednesday, August 27, 2008
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The 2009 Design and Verification Conference (DVCon), sponsored by Accellera, is now accepting paper, panel and tutorial submissions. Proposals that reflect real experiences using hardware design and verification languages, advanced tools and methodologies are encouraged. Paper and panel proposals are due September 19, 2008.

DVCon 2009 will be held February 24-26 at the DoubleTree Hotel in San Jose, California. It is the premier conference for the functional design and verification of electronic systems. The 2008 conference boasted a record number of attendees and exhibitors. As the industry has grown and evolved, verification remains one of the most complex areas of design and the conference has kept pace in addressing key challenges and solutions. DVCon will continue to provide attendees with an unparalleled forum where technology leaders, practicing engineers, academia, and the vendor community can share the latest practical and leading-edge techniques, technologies and methods.

Panel Proposals: To submit a panel idea, please submit an abstract and a list of panelist candidates via email to Kathy Embler at MP Associates at kathy@mpassociates.com.

Sponsored tutorial proposals are due October 3, 2008
A limited number of sponsored tutorials are available. Submit all proposals to Kathy Embler at MP Associates at kathy@mpassociates.com.

Accellera sponsors DVCon. Accellera is an industry consortium dedicated to the development and standardization of EDA languages, methods and formats, including design and verification languages.

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