Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced its SPB 16.2 release, which focuses aggressively on addressing current and emerging chip package design challenges. This latest release delivers advanced IC package/system-in-package (SiP) miniaturization, design cycle reduction and DFM-driven design, along with a new power integrity modeling solution. These new capabilities can boost productivity of digital, analog, RF and mixed-signal IC package designers involved in single and multi-die packages/SiPs.
Design teams can expect improvements in the reduction in overall package size through the introduction of rules and constraint-driven automation capabilities that address the design methodology of high-density interconnect (HDI) substrate manufacturing that is a key enabler for miniaturization and increased functional density. Overall design time can be reduced through the enablement of team-based design, where multiple designers can work concurrently on the same design in order to reduce design cycle times and speed time to market.
With today’s focus on low-power design, especially in wireless and battery-powered devices, an efficient package power delivery network (PDN) is critical for meeting power-management goals. The new power integrity technology allows designers to efficiently address the power-delivery design goals of sufficiency, efficiency and stability.
“Leading-edge complex high-speed ICs create very challenging IC package designs, both from a physical implementation and a signal and power integrity aspect,” said Kevin Roselle, chief technology officer at Bayside Design. “With today’s focus on product miniaturization, increased designer productivity and efficient PDN design, we feel that SPB16.2 will help designers better address their design challenges.”
In addition, through an agreement with Kulicke & Soffa, a manufacturing equipment leader, Cadence enables DFM-driven wirebond design by using Kulicke & Soffa-verified wirebond IP profile libraries, increasing yield and reducing manufacturing delays.
“With wirebond packages becoming increasingly complex, the designer is being challenged to design-in DFM compliance in order to avoid manufacturing issues,” said Paul Reid, product marketing manager at Kulicke & Soffa. “By joining forces, we can now deliver DFM-proven loop profile libraries to the design community’s desktop.”
“This new release provides significant enhancements to our IC Packaging and SiP technologies, and we’re glad to see companies such as Bayside Design benefiting from its use,” said Steve Kamin, product marketing group director at Cadence. “We are committed to evolving our technology and building relationships with key design-chain players in order to maintain our leadership role in helping designers meet and exceed their design goals.”
SPB 16.2 will be available in Q4 2008. Customers can see demos of Allegro PCB and IC packaging/SiP flows at the CDNLive! Silicon Valley conference Sept. 9-11, or enroll in a techtorial on SPB 16.2 on Sept. 8. SPB 16.2 also will be demonstrated at the EMA booth at the PCB West in Santa Clara Sept 14-19.
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
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