Sonics Inc., a premier supplier of system-on-chip SMART Interconnect solutions, announced the availability of the SonicsSX SMART Interconnect solution. Designed for SoCs requiring high quality, high definition, or HQHD, video support, SonicsSX accelerates video performance and eases global integration of intellectual property cores and subsystems onto a single chip. SonicsSX also contains a new Interleaved Multichannel Technology (IMT) that enables SoC architectures to seamlessly transition from single to multiple DRAM channels, or multichannel, while automatically balancing the traffic among the channels. IMT operates transparently to software and hardware.
To improve image quality and support higher resolutions, HQHD video requires the adoption of upgraded video protocols, more image resolution enhancement, and scaling up to 120Hz. This is causing a shift towards utilizing matched groups of processors and supporting elements, or subsystems, that supply the on-chip processing required to achieve HQHD video performance. The transition to subsystems means that SoC architectures must now become hierarchical. Interconnects within the subsystems are needed to support the local data throughput requirements of the subsystems, and a global interconnect is required for subsystem integration onto a single chip and to manage the global data throughput requirements. Increased processing and subsystem integration complexities result in the need to significantly increase external memory performance, which is now the primary design challenge for HQHD video SoCs.
SonicsSX is built on the proven architecture of previous SMART Interconnect solutions. It contains all the advanced fabric features and data flow services, such as universal IP core connectivity, non-blocking multithreaded data flow, and power, security and system error management, that are presently powering over 250 million production SoCs containing other SMART Interconnect solutions, such as SonicsMX[tm] and SonicsLX[tm].
To address increased processing for HQHD, SonicsSX offers network-on-chip (NoC) capabilities for higher operating clock frequencies, native support for 2D data transactions and an expanded data bus to 256 bits. SonicsSX also offers Interleaved Multichannel Technology, which enables SoC developers to transition their architectures from single to multiple DRAM channels, while avoiding the complexities associated with multichannel memory management. IMT utilizes an innovative memory interleaving methodology as a foundation for managing up to 8 external DRAM channels. User-controlled interleaving addresses the key challenge associated with adopting multichannel architectures: ensuring that the memory traffic is divided evenly among the channels. The addition of these new features increases interconnect performance when using SonicsSX from the 2-4 gigabytes per second required for high-definition video, to up to 16 gigabytes per second, per port for HQHD video.
SonicsSX also supports the Practical Globally Asynchronous Locally Synchronous (GALS) approach that is part of any SMART Interconnect solution. Practical GALS enables SoC developers to extend the capabilities of SonicsSX to include voltage and domain isolation on an IP core or subsystem basis, which further facilitates low power and higher performance. Practical GALS does not disturb SoC design flows, which is typically the case when implementing asynchronous functionality.
“SoC architecture is at a major inflection point. Almost all high-volume SoCs must move to HQHD,” said Drew Wingard CTO, Sonics. “But the massive complexities associated with a transition to HQHD means that more conventional architecture approaches will have to be abandoned because they will not reach the memory performance requirements. SonicsSX with IMT offers a flexible low overhead approach to reaching HQHD memory performance, while eliminating the complexities of multichannel memory management design. Easy access to IMT within the well-proven SMART Interconnect solution approach provides a seamless transition to multichannel memory management and hierarchical SoCs.”
SystemC models are available for advanced architecture modeling using SonicsSX. As a member of the SMART Interconnect family, RTL configuration and modeling is available through the SonicsStudio[tm] Development Environment, enabling SoC developers to complete data flow analysis for SonicsSX during the architecture phase of a product development cycle. Predictable high-performance data flows, including those related to the multichannel memory subsystem, that are available before the hardware and software development phase begins, significantly reduces the development time and project risks for hardware and software teams.
Sonics Inc. is a premier supplier of SMART Interconnect solutions that deliver high SoC design predictability and increased design efficiency. Major semiconductor and systems companies including Broadcom, Samsung, Texas Instruments and Toshiba have applied Sonics’ SMART Interconnect solutions in leading products in the wireless, digital multimedia and communications markets. Sonics is a privately-held company funded by Cadence Design Systems, Toshiba Corporation, Samsung Ventures and venture capital firms Investar Capital, TL Ventures, Smart Technology Ventures, and Easton Hunt Capital, among others.
®Sonics Inc., the company’s logo, IMT, SonicsSX, SonicsStudio and SMART Interconnect are registered trademarks of Sonics Inc.