TEK Microsystems Unveils Neptune-V5 VITA 41-compliant Digitizer Board

TEK Microsystems, Inc., the leading supplier of VXS-based digitizers has announced the Neptune-V5 6U VITA 41-compliant dual channel high-speed digitizer board. Designed to meet the needs of demanding sensor-processing applications across a range of environments, the Neptune-V5 employs three Virtex®-5 processors, advanced DDR3 SDRAM, and the latest communications technologies available. Full ruggedization has been designed into the architecture providing full support for harsh environments.

TEK Microsystems Neptune-V5 VITA 41 Digitizer Board“The QuiXilica architecture is based on careful selection of the right features in the right places to solve the problem, as opposed to “checking the box” and using power, space and gates for capabilities that don’t move the solution forward,” comments TEK Microsystems, Inc. president and CTO Andrew Reddig. “Our architecture is designed to match the demands of streaming sensor I/O processing requirements. The Neptune-V5 integrates well into network and fabric centric systems, but we don’t impose the overhead of a switched fabric all the way back to the front end sensor processing nodes. Instead, we use straightforward data flow mechanisms with the highest possible performance where speed is critical, and then add network oriented endpoint IP at the point that scalability adds value.”

The Neptune-V5 uses three Xilinx Virtex-5 FPGAs, DDR3 SDRAM and the latest flexible I/O communication modules (SFP+ and QSFP). Firmware and software support for a range of open standards and protocols are provided including Gigabit Ethernet, Serial FPDP (ANSI VITA 17.1 and 17.2) and Fibre Channel. For inter-FPGA and inter-board communications, protocol support is provided for Xilinx Aurora and PCI Express. Our approach to the architecture focuses on the sensor IO processing and allows us to more efficiently utilize three V-5 processors than competitive offerings of up to seven FPGAs resulting in a lower price point and reduced power consumption.

A very broad range of analog sensor I/O configurations provide compatibility with the widest range of analog signal options, addressing multi-channel, high resolution sampled data requirements at 2 Gsps (Gigasamples per second) and beyond.

Neptune-V5 Overview
Neptune-V5 use three Xilinx Virtex-5 FPGAs to provide maximum high bandwidth processing and system configuration flexibility. Depending on the application, customers can select from three Virtex-5 platforms:

  • Virtex-5 LXT Platform – Optimized for high-performance logic with low-power serial connectivity
  • Virtex-5 SXT Platform – Optimized for DSP and memory-intensive applications with low-power serial connectivity
  • Virtex-5 FXT Platform – Optimized for embedded processing and memory-intensive applications with highest-speed serial connectivity

In a typical configuration shown below two Xilinx Virtex-5 SX95T FPGAs interface between the ADC¹s, memory and I/O resources to provide the user with a platform for implementing high performance real time processing. The IO FPGAs A and B can be any Virtex-5 FF1136 device. The back-end Comms FPGA can be any FF1136 or 1738 device which provides additional resources for implementing DSP and interfaces to the VXS backplane. All FPGAs are interconnected by wide parallel LVDS busses via MGTs.

  2 x SX95T +
1 x LX110T
2 x SX95T +
1 x FX100T
3 x FX100T
V5 Slices 46,720 31,040 48,000
18Kb BRAMs 1,272 1,432 1,368
Ethernet MACs 12 12 12
DSP48s 1344 1,536 768
PCI Express Endpoints 3 5 9

The FPGA can access two banks of DDR3 SDRAM of 512 MB each (1 GB total per FPGA). The DDR3 SDRAM uses 17% less power than DDR2. Memory and FPGAs are interconnected using multiple high bandwidth parallel and high-speed serial interconnections; thus data can be available within the processing chain as needed to meet a wide range of application requirements.

Two e2v AT84AS008 10-bit Analog to Digital Converters (ADCs) are provided on the Neptune-V5, each capable of operating at sampling rates of 2.2 Gsps. Control functions on each ADC, such as sampling point adjustment, gain adjustment, and input DC bias adjustment can be accessed from the FPGA, through a two-wire, I2C-compatible interface. Trigger firmware can be implemented in the FPGA to fully synchronize data captures between multiple ADC channels on the same board or across multiple Neptune-V5 boards if required.

Inter-board and system communication requirements are met using either backplane connections or multiple front-panel high speed serial Quad Small Form-Factor Pluggable (QSFP) and Small Form-Factor Pluggable (SFP+) modules which provide eight and six high speed serial links respectively operating at up to 6.5 Gb/s. Utilizing the embedded communication functions, as well as Tekmicro¹s QuiXilica core and software library support (QuiXtream), the QuiXilica V5 Family supports the latest generation of Open Standard I/O protocols such as Gigabit Ethernet, Serial FPDP (ANSI VITA 17.1 & 17.2), PCI Express, Xilinx Aurora and Fibre Channel.

Neptune-V5 boards operate effectively in laboratory, rugged air-cooled, and rugged conduction-cooled environments to meet the needs of deployed applications.

QuiXilica V5 has been developed to meet the requirements of data-flow sensor I/O applications making QuiXilica V5 VXS boards the ideal solution for the latest generation of front-end sensor processor development.

About TEK Microsystems, Inc.
Founded in 1981 and headquartered in Chelmsford, Massachusetts, TEK Microsystems, Inc., designs, manufactures and markets a wide range of advanced high-performance boards and systems for embedded real-time data acquisition, data conversion, storage and recording. The Company provides both commercial and rugged grade products which are used in real-time systems designed for applications such as reconnaissance, electronic warfare, signals intelligence, mine detection, medical imaging, radar, sonar, semiconductor inspection and seismic research.